Title:
DATA PROCESSING APPARATUS FOR TRANSMITTING/RECEIVING COMPRESSED PIXEL DATA GROUPS VIA MULTIPLE DISPLAY PORTS OF DISPLAY INTERFACE AND RELATED DATA PROCESSING METHOD
Kind Code:
A1


Abstract:
A data processing apparatus includes a compression circuit, a rate controller, and an output interface. The compression circuit generates a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture. The rate controller applies bit-rate control to each compression operation, wherein the rate controller adjusts the bit-rate control according to a position of each pixel boundary between different pixel groups. The output interface outputs the compressed pixel data groups via a plurality of display ports of a display interface, respectively.



Inventors:
Ju, Chi-cheng (Hsinchu City, TW)
Liu, Tsu-ming (Hsinchu City, TW)
Application Number:
14/335956
Publication Date:
02/19/2015
Filing Date:
07/21/2014
Assignee:
MEDIATEK INC.
Primary Class:
International Classes:
G09G5/00
View Patent Images:
Related US Applications:



Primary Examiner:
TUNG, KEE M
Attorney, Agent or Firm:
NORTH AMERICA INTELLECTUAL PROPERTY CORPORATION (NEW TAIPEI CITY, TW)
Claims:
What is claimed is:

1. A data processing apparatus, comprising: a compression circuit, configured to generate a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture; a rate controller, configured to apply bit-rate control to each compression operation, wherein the rate controller adjusts the bit-rate control according to a position of each pixel boundary between different pixel groups; and an output interface, configured to output the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

2. The data processing apparatus of claim 1, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

3. The data processing apparatus of claim 1, wherein concerning a specific pixel boundary between a first pixel group and a second pixel group, the rate controller is configured to increase an original bit budget assigned to a first compression unit by an adjustment value and decrease an original bit budget assigned to a second compression unit by the adjustment value; the first compression unit and the second compression unit are adjacent compression units in any of the first pixel group and the second pixel group; and the first compression unit is nearer to the specific pixel boundary than the second compression unit.

4. A data processing apparatus, comprising: a compression circuit, configured to generate a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group according to a compression order, wherein the pixel group includes a portion of a plurality of pixels in a picture, and the compression order is set according to a position of a pixel boundary between the pixel group and an adjacent pixel group; and an output interface, configured to output the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

5. The data processing apparatus of claim 4, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

6. The data processing apparatus of claim 4, wherein the compression circuit is configured to compress a first compression unit prior to compressing a second compression unit, and compress a third compression unit prior to compressing a fourth compression unit; the first compression unit and the second compression unit are adjacent compression units in the pixel group, and the first compression unit is nearer to the pixel boundary than the second compression unit; and the third compression unit and the fourth second compression unit are adjacent compression units in the adjacent pixel group, and the third compression unit is nearer to the pixel boundary than the fourth compression unit.

7. A data processing apparatus, comprising: a compression circuit, configured to generate a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture, and at least two pixel groups have overlapped pixels; and an output interface, configured to output the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

8. The data processing apparatus of claim 7, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

9. A data processing apparatus, comprising: an input interface, configured to receive an input bitstream from a display port of a display interface, and un-pack the input bitstream into a compressed pixel data group of a picture; and a de-compressor, configured to de-compress the compressed pixel data group to generate a preliminary de-compressed pixel data group, and discard a portion of the preliminary de-compressed pixel data group that corresponds to pixels beyond a target display region driven by the data processing apparatus, wherein the target display region corresponds to a portion of the picture.

10. The data processing apparatus of claim 9, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

11. A data processing method, comprising: generating a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture; performing bit-rate control which is adjusted according to a position of each pixel boundary between different pixel groups; and outputting the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

12. The data processing method of claim 11, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

13. The data processing method of claim 11, wherein concerning a specific pixel boundary between a first pixel group and a second pixel group, the bit-rate control increases an original bit budget assigned to a first compression unit by an adjustment value and decreases an original bit budget assigned to a second compression unit by the adjustment value; the first compression unit and the second compression unit are adjacent compression units in any of the first pixel group and the second pixel group; and the first compression unit is nearer to the specific pixel boundary than the second compression unit.

14. A data processing method, comprising: generating a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group according to a compression order, wherein the pixel group includes a portion of a plurality of pixels in a picture, and the compression order is set according to a position of a pixel boundary between the pixel group and an adjacent pixel group; and outputting the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

15. The data processing method of claim 14, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

16. The data processing method of claim 14, wherein the step of generating the compressed pixel data groups comprises: compressing a first compression unit prior to compressing a second compression unit; and compressing a third compression unit prior to compressing a fourth compression unit; wherein the first compression unit and the second compression unit are adjacent compression units in the pixel group, and the first compression unit is nearer to the pixel boundary than the second compression unit; and the third compression unit and the fourth second compression unit are adjacent compression units in the adjacent pixel group, and the third compression unit is nearer to the pixel boundary than the fourth compression unit.

17. A data processing method, comprising: generating a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture, and at least two pixel groups have overlapped pixels; and outputting the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

18. The data processing method of claim 17, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

19. A data processing method, comprising: receiving an input bitstream from a display port of a display interface, and un-packing the input bitstream into a compressed pixel data group of a picture; and de-compressing the compressed pixel data group to generate a preliminary de-compressed pixel data group, and discard a portion of the preliminary de-compressed pixel data group that corresponds to pixels beyond a target display region to be driven, wherein the target display region corresponds to a portion of the picture.

20. The data processing method of claim 19, wherein the display interface is a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA).

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No. 61/865,345, filed on Aug. 13, 2013 and incorporated herein by reference.

BACKGROUND

The disclosed embodiments of the present invention relate to transmitting and receiving data over a display interface, and more particularly, to a data processing apparatus for transmitting/receiving compressed pixel data groups of a picture via multiple display ports of a display interface and a related data processing method.

A display interface is disposed between a first chip and a second chip to transmit display data from the first chip to the second chip for further processing. For example, the first chip may be a host application processor, and the second chip may be a driver integrated circuit (IC). The display data may be single view data for two-dimensional (2D) display or multiple view data for three-dimensional (3D) display. When a display panel supports a higher display resolution, 2D/3D display with higher resolution can be realized. Hence, the display data transmitted over the display interface would have a larger data size/data rate, which increases the power consumption of the display interface inevitably. If the host application processor and the driver IC are both located at a portable device (e.g., a smartphone) powered by a battery device, the battery life is shortened due to the increased power consumption of the display interface. Thus, there is a need for an innovative design which can effectively reduce the power consumption of the display interface.

SUMMARY

In accordance with exemplary embodiments of the present invention, a data processing apparatus for transmitting/receiving compressed pixel data groups of a picture via multiple display ports of a display interface and a related data processing method are proposed.

According to a first aspect of the present invention, an exemplary data processing apparatus is disclosed. The exemplary data processing apparatus includes a compression circuit, a rate controller and an output interface. The compression circuit is configured to generate a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture. The rate controller is configured to apply bit-rate control to each compression operation, wherein the rate controller adjusts the bit-rate control according to a position of each pixel boundary between different pixel groups. The output interface is configured to output the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

According to a second aspect of the present invention, an exemplary data processing apparatus is disclosed. The exemplary data processing apparatus includes a compression circuit and an output interface. The compression circuit is configured to generate a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group according to a compression order, wherein the pixel group includes a portion of a plurality of pixels in a picture, and the compression order is set according to a position of a pixel boundary between the pixel group and an adjacent pixel group. The output interface is configured to output the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

According to a third aspect of the present invention, an exemplary data processing apparatus is disclosed. The exemplary data processing apparatus includes a compression circuit and an output interface. The compression circuit is configured to generate a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture, and at least two pixel groups have overlapped pixels. The output interface is configured to output the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

According to a fourth aspect of the present invention, an exemplary data processing apparatus is disclosed. The exemplary data processing apparatus includes an input interface and a de-compressor. The input interface is configured to receive an input bitstream from a display port of a display interface, and un-pack the input bitstream into a compressed pixel data group of a picture. The de-compressor is configured to de-compress the compressed pixel data group to generate a preliminary de-compressed pixel data group, and discard a portion of the preliminary de-compressed pixel data group that corresponds to pixels beyond a target display region driven by the data processing apparatus, wherein the target display region corresponds to a portion of the picture.

According to a fifth aspect of the present invention, an exemplary data processing method is disclosed. The exemplary data processing method includes: generating a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture; performing bit-rate control which is adjusted according to a position of each pixel boundary between different pixel groups; and outputting the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

According to a sixth aspect of the present invention, an exemplary data processing method is disclosed. The exemplary data processing method includes: generating a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group according to a compression order, wherein the pixel group includes a portion of a plurality of pixels in a picture, and the compression order is set according to a position of a pixel boundary between the pixel group and an adjacent pixel group; and outputting the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

According to a seventh aspect of the present invention, an exemplary data processing method is disclosed. The exemplary data processing method includes: generating a plurality of compressed pixel data groups, each derived from applying a compression operation to pixel data of a pixel group, wherein the pixel group includes a portion of a plurality of pixels in a picture, and at least two pixel groups have overlapped pixels; and outputting the compressed pixel data groups via a plurality of display ports of a display interface, respectively.

According to an eighth aspect of the present invention, an exemplary data processing method is disclosed. The exemplary data processing method includes: receiving an input bitstream from a display port of a display interface, and un-packing the input bitstream into a compressed pixel data group of a picture; and de-compressing the compressed pixel data group to generate a preliminary de-compressed pixel data group, and discard a portion of the preliminary de-compressed pixel data group that corresponds to pixels beyond a target display region to be driven, wherein the target display region corresponds to a portion of the picture.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention.

FIG. 2 is a diagram of an application processor shown in FIG. 1 according to an embodiment of the present invention.

FIG. 3 is a diagram of one of driver ICs shown in FIG. 1 according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a rate control mechanism according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a position-aware rate control mechanism according to an embodiment of the present invention.

FIG. 6 is a flowchart illustrating a control and data flow of the data processing system shown in FIG. 1 according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a modified compression mechanism according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating another control and data flow of the data processing system shown in FIG. 1 according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating a pixel data splitting operation performed by a mapper based on another pixel data grouping design.

FIG. 10 is a flowchart illustrating yet another control and data flow of the data processing system shown in FIG. 1 according to an embodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

The present invention proposes applying data compression to a display data and then transmitting a compressed display data over a display interface. As the data size/data rate of the compressed display data is smaller than that of the original un-compressed display data, the power consumption of the display interface is reduced correspondingly. When the display interface is required to use a plurality of display ports for compressed data transmission, the pixel data of one picture may be split into a plurality of pixel data groups, the pixel data groups may be compressed into a plurality of compressed pixel data groups, and the compressed pixel data groups may be transmitted via the display ports respectively. The present invention further proposes an image quality improvement scheme which is capable of making a reconstructed picture have better image quality on each pixel boundary of de-compressed pixel data groups, where each de-compressed pixel data group is obtained based on a de-compression result of one compressed pixel data group transmitted via one display port. Further details will be described as below.

FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention. The data processing system 100 includes a plurality of data processing apparatuses such as one application processor (AP) 102 and a plurality of driver integrated circuits (ICs) 104_1-104_N. The driver ICs 104_1-104_N serve as display drivers of a display panel 106, where the number of driver ICs 104_1-104_N depends on the actual driving requirement of the display panel 106. For example, the display panel 106 may be a high-definition (HD) panel (e.g., 1080P panel) or an ultra-high definition (UHD) panel (e.g., 4K2K panel). To alleviate the bandwidth and fan-out requirement between the display driver and the display panel, a display screen 107 of the display panel 106 may be divided into a plurality of display regions R1-RN, and each of the display regions R1-RN is driven by one of the driver ICs 104_1-104_N. In other words, each of the driver ICs 104_1-104_N is only responsible of driving a portion of the display screen 107, and therefore does not need to transmit all display data of a complete picture to the display panel 106.

The application processor 102 and the driver ICs 104_1-104_N may be implemented in different chips, and the application processor 102 may communicate with the driver ICs 104_1-104_N via a plurality of display ports P1-PN of a display interface 103, respectively. In this embodiment, the display interface 103 may be a display serial interface (DSI) standardized by a Mobile Industry Processor Interface (MIPI) or an embedded display port (eDP) standardized by a Video Electronics Standards Association (VESA). Each of the driver ICs 104_1-104_N receives partial compressed display data of one picture IMG from the application processor 102, and generates partial de-compressed display data to one display region of the display screen 107.

The application processor 102 is coupled between an external data source (not shown) and the display interface 103, and supports compressed data transmission. The application processor 102 receives the input display data from the external data source (e.g., a camera sensor, a memory card or a wireless receiver), generates a plurality of partial compressed display data, and transmits the partial compressed display data to the driver ICs 104_1-104_N via display ports P1-PN of the display interface 103, where the input display data may be image data or video data that includes pixel data DI of a plurality of pixels of one picture IMG to be displayed on the display panel 106.

Please refer to FIG. 2, which is a diagram of the application processor 102 shown in FIG. 1 according to an embodiment of the present invention. The application processor 102 includes a display controller 111, an output interface 112 and a processing circuit 113. The processing circuit 113 includes circuit elements required for processing the pixel data DI of the picture IMG to generate a plurality of compressed pixel data groups D1′-DN′. For example, the processing circuit 113 has a compression circuit 114, a rate controller 115, and other circuitry 116. The processing circuit 113 includes a mapper 114 and a plurality of compressors 118_1-118_N. The other circuitry 116 may have a display processor, additional image processing element(s), etc. The display processor may perform image processing operations, including scaling, rotating, etc. For example, the input display data provided by an external data source (not shown) may be bypassed or processed by the additional image processing element(s) located before the display processor to generate a source display data, and then the display processor may process the source display data to generate the pixel data DI to the mapper 117. In other words, the pixel data DI to be processed by the mapper 117 may be directly provided from the data source or indirectly obtained from the input display data provided by the data source. The present invention has no limitation on the source of the pixel data DI.

The mapper 114 acts as a splitter, and is configured to receive the pixel data DI of one picture IMG and split the pixel data DI of one picture IMG into a plurality of pixel data groups D1-DN according to a pixel data group setting DGSET. The display controller 111 is configured to control the operation of the processing circuit 113. As can be seen from FIG. 1, there are N driver ICs 104_1-104_N coupled to the same application processor 102; and there are N display regions R1-RN driven by the N driver ICs 104_1-104_N, respectively. As shown in FIG. 1, the width of the picture IMG is W, and the height of the picture IMG is H. Supposing that the display regions R1-RN have the same size, each of the image partitions A1-AN may have a resolution of (W/N)×H. It should be noted that this is for illustrative purposes only. In an alternative design, the display regions R1-RN may have different sizes, and the image partitions A1-AN may have different resolutions. Moreover, the horizontal display region partitioning applied to the display screen 107 and the horizontal image partitioning applied to the picture IMG are not meant to be limitations of the present invention. In an alternative design, the vertical display region partitioning may be applied to the display screen 107, thus resulting in multiple display regions arranged vertically in the display screen 107; and the vertical image partitioning may be applied to the picture IMG, thus resulting in multiple image partitions arranged vertically in the picture IMG. Since the display regions R1-RN will be used to display image contents of a plurality of image partitions in the same picture respectively, the pixel data grouping setting DGSET corresponding to the exemplary arrangement of the image partitions A1-AN shown in FIG. 1 may be decided by the display controller 111.

In an exemplary pixel data grouping design, the pixel data grouping setting DGSET defines selection of non-overlapped pixels for generating each pixel data group. Hence, any pixel included in one pixel group is excluded from other pixel groups. For example, based on the pixel data grouping setting DGSET, the mapper 117 regards all pixels belonging to one image partition as one pixel group, and only gathers pixel data of the pixel group as one pixel data group. Hence, the pixel data group D1 only includes pixel data of one pixel group including all pixels belonging to the image partition A1, and the pixel data group DN only includes pixel data of another pixel group including all pixels belonging to the image partition AN.

The compressors 118_1-118_N compress the pixel data groups D1-DN to generate compressed pixel data groups D1′-DN′, respectively. The rate controller 115 is configured to apply bit rate control to each of the compressors 118_1-118_N for controlling a bit budget allocation per compression unit. In this way, each of the compressed pixel data groups D1′-DN′ is generated at a desired bit rate. In this embodiment, compression operations performed by the compressors 118_1-118_N are independent of each other, thus enabling rate control with data parallelism.

The output interface 112 is configured to refer to the transmission protocol of the display interface 103 to pack/packetize the compressed pixel data groups D1′-DN′ into a plurality of output bitstreams BS1-BSN, respectively; and transmit the output bitstreams BS1-BSN to the driver ICs 104_1-104_N via a plurality of display ports P1-PN of the display interface 103, respectively.

When the application processor 102 transmits one partial compressed display data (e.g., one of compressed pixel data groups D1′-DN′) to one driver IC, the driver IC receives the partial compressed display data from one display port of the display interface 103, and de-compress the partial compressed display data to generate one partial de-compressed display data (e.g., one of de-compressed pixel data groups D1″-DN″) for driving a portion of the display screen 107. Each of the driver ICs 104_1-104_N communicates with the application processor 102 via the display interface 103, and may have the same circuit configuration. For clarity and simplicity, only one of the driver ICs 104_1-104_N is detailed as below.

Please refer to FIG. 3, which is a diagram illustrating the driver IC 104_1 shown in FIG. 1 according to an embodiment of the present invention. The driver IC 104_1 is coupled between the display interface 103 and the display port P1 of the display panel 106, and supports compressed data reception. In this embodiment, the driver IC 104_1 includes a driver IC controller 121, an input interface 122 and a processing circuit 123. The input interface 122 is configured to receive an input bitstream (i.e., the bitstream BS1 transmitted via display port P1), and un-pack/un-packetize the input bitstream into a compressed pixel data group of one picture (e.g., compressed pixel data group D1′ packed in the bitstream BS1). It should be noted that, if there is no error introduced during the data transmission, the compressed pixel data group un-packed/un-packetized from the input interface 122 should be identical to the compressed pixel data groups D1′ received by the output interface 112.

The driver IC controller 121 is configured to control the operation of the processing circuit 123. The processing circuit 123 may include circuit elements required for driving one display region R1 of the display panel 106. For example, the processing circuit 123 has one de-compressor 124 and other circuitry 125. The other circuitry 125 may have a display buffer, additional image processing element(s), etc. The de-compressor 124 generates a de-compressed pixel data group D1″ based on a de-compression result of the compressed pixel data group un-packed/un-packetized from the input interface 122, where the partial display data to be displayed on the display region R1 of the display screen 107 is derived from the de-compressed pixel data group D1″. When the pixel data grouping design mentioned above is employed by the application processor 102, the de-compressor 124 directly obtains the de-compressed pixel data group D1″ by de-compressing the compressed pixel data group un-packed/un-packetized from the input interface 122.

The pixel data splitting operation performed by the mapper 117 shown in FIG. 2 is to generate multiple pixel data groups that will undergo rate-controlled compression independently for compressed data transmission over multiple display ports P1-PN of the display interface 103. However, it is possible that pixel data of adjacent pixel lines (e.g., pixel rows or pixel columns) in the original picture are categorized into different pixel data groups. The rate control generally optimizes the bit rate in terms of pixel context rather than pixel positions. The pixel boundary may introduce artifacts since the rate control is not aware of the boundary position.

Consider a case where the pixel data grouping setting DGSET defines selection of non-overlapped pixels for generating each pixel data group. Thus, the mapper 117 gathers pixel data of all pixels belonging to one image partition as one pixel data group only. The rate control applied to the pixel data group of the image partition A1 is independent of the rate control applied to the pixel data group of the image partition A2, and the rate control applied to the pixel data group of the image partition AN-1 is independent of the rate control applied to the pixel data group of the image partition AN. Please refer to FIG. 4, which is a diagram illustrating a rate control mechanism according to an embodiment of the present invention. Based on the pixel data grouping setting DGSET, the mapper 117 splits one pixel line (e.g., one pixel row in this example shown in FIG. 4) composed of pixels P1-PW into a plurality of pixel sections S1-SN each having multiple pixels. The pixel sections S1-SN correspond to the image partitions A1-AN, respectively. The pixel section S1 is compressed in an order from P1 to PI, where I=W/N; the pixel section S2 is compressed in an order from PI+1 to PJ, where J=2×(W/N); the pixel section SN-1 is compressed in an order from PK+1 to PL, where K=(N−2)×(W/N) and L=(N−1)×(W/N); and the pixel section SN is compressed in an order from PL+1 to PW. Concerning the pixels PI and PI+1 on opposite sides of a pixel boundary between pixel sections S1 and S2, the pixel PI may be part of a compression unit with one bit budget allocation, and the pixel PI+1 may be part of another compression unit with a different bit budget allocation. Similarly, concerning the pixels PL and PL+1 on opposite sides of a pixel boundary between pixel sections SN-1 and SN, the pixel PL may be part of a compression unit with one bit budget allocation, and the pixel PL+1 may be part of another compression unit with a different bit budget allocation. The difference between the bit budget allocations of compression units on opposite of a pixel boundary may be large. As a result, the rate controller 115 may allocate bit rates un-evenly on the pixel boundary, thus resulting in degraded image quality on the pixel boundary in a reconstructed picture. To avoid or mitigate the image quality degradation caused by artifacts on the pixel boundary, the present invention therefore proposes a position-aware rate control mechanism which optimizes the bit budget allocation in terms of pixel positions.

FIG. 5 is a diagram illustrating a position-aware rate control mechanism according to an embodiment of the present invention. As shown in FIG. 5, there are compression units CU1 and CU2 on one side of a pixel boundary and compression units CU3 and CU4 on the other side of the pixel boundary. The compression units CU1 and CU2 belong to one pixel group PG1, and the compression unit CU1 is nearer to the pixel boundary than the compression unit CU2. The compression units CU3 and CU4 belong to another pixel group PG2, and the compression unit CU3 is nearer to the pixel boundary than the compression unit CU4. For example, the pixel data of pixels in the pixel group PG1 may be compressed into one compressed pixel data group D1′ (or DN-1′), and the pixel data of pixels in the pixel group PG2 may be compressed into another compressed pixel data group D2′ (or DN′). In one exemplary embodiment, each of the compression units CU1-CU4 may include 4×2 pixels, and the compression units CU1-CU4 may be horizontally or vertically adjacent in one picture. When the position-aware rate control mechanism is activated, the rate controller 115 may be configured to adjust the bit-rate control (i.e., bit budget allocation) according to a position of each pixel boundary between different pixel groups. For example, the rate controller 115 increases an original bit budget BBori_CU1 assigned to the compression unit CU1 by an adjustment value Δ1 (Δ1>0) to thereby determine a final bit budget BBtar_CU1, and decreases an original bit budget BBori_CU2 assigned to the compression unit CU2 by the adjustment value Δ1 to thereby determine a final bit budget BBtar_CU2. In addition, the rate controller 115 increases an original bit budget BBori_CU3 assigned to the compression unit CU3 by an adjustment value Δ2 (Δ2>0) to thereby determine a final bit budget BBtar_CU3, and decreases an original bit budget BBori_CU4 assigned to the compression unit CU4 by the adjustment value Δ2 to thereby determine a final bit budget BBtar_CU4. The adjustment value Δ2 may be equal to or different from the adjustment value Δ1, depending upon actual design consideration. Since the proposed position-aware rate control tends to set a larger bit budget near the pixel boundary, the artifacts on the pixel boundary can be reduced. In this way, the image quality around the pixel boundary in a reconstructed picture can be improved.

FIG. 6 is a flowchart illustrating a control and data flow of the data processing system shown in FIG. 1 according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 6. The exemplary control and data flow may be briefly summarized by following steps.

Step 602: Split pixel data of a plurality of pixels of one picture into a plurality of pixel data groups.

Step 604: Apply rate control to each of a plurality of compressors according to pixel boundary positions.

Step 606: Generate a plurality of compressed pixel data groups by using the compressors to compress the pixel data groups, respectively.

Step 608: Pack/packetize the compressed pixel data groups into a plurality of output bitstreams, respectively.

Step 610: Transmit the output bitstreams via a plurality of display ports of a display interface, respectively.

Step 612: Receive an input bitstream from the display interface.

Step 614: Un-pack/un-packetize the input bitstream into a compressed data group.

Step 616: Generate a de-compressed pixel data group by using a de-compressor to de-compress the compressed pixel data group.

It should be noted that steps 602-610 are performed by the application processor (AP) 102, and steps 612-616 are performed by one of the driver ICs 104_1-104_N. As a person skilled in the art can readily understand details of each step shown in FIG. 6 after reading above paragraphs, further description is omitted here for brevity.

As can be seen from FIG. 4, the rate control applied to the pixel section S1 of a pixel line (e.g., pixel row or pixel column) is independent of the rate control applied to the pixel section S2 of the same pixel line. The pixel section S1 is compressed in an order from P1 to PI, and the pixel section S2 is compressed in an order from PI+1 to PJ. The pixel section SN-1 is compressed in an order from PK+1 to PL, and the pixel section SN is compressed in an order from PL+1 to PW. In other words, each pixel section located at the same pixel line is compressed in the same compression order, as shown in FIG. 4. As a result, the bit budget allocation condition for the pixel PI (which is the last compressed pixel in the pixel section S1) may be different from the bit budget allocation condition for the pixel PI+1 (which is the first compressed pixel in the pixel section S2); and the bit budget allocation condition for the pixel PL (which is the last compressed pixel in the pixel section SN-1) may be different from the bit budget allocation condition for the pixel PL+1 (which is the first compressed pixel in the pixel section SN). To avoid or reduce artifacts on the pixel boundary, the present invention further proposes a modified compression mechanism with compression orders set based on pixel boundary positions.

Please refer to FIG. 7, which is a diagram illustrating a modified compression mechanism according to an embodiment of the present invention. As shown in FIG. 7, there are compression units CU1 and CU2 on one side of a pixel boundary and compression units CU3 and CU4 on the other side of the pixel boundary. The compression units CU1 and CU2 belong to one pixel group PG1, and the compression unit CU1 is nearer to the pixel boundary than the compression unit CU2. The compression units CU3 and CU4 belong to another pixel group PG2, and the compression unit CU3 is nearer to the pixel boundary than the compression unit CU4. For example, the pixel data of pixels in the pixel group PG1 may be compressed into one compressed pixel data group D1′ (or DN-1′), and the pixel data of pixels in the pixel group PG2 may be compressed into another compressed pixel data group D2′ (or DN′).

In one exemplary embodiment, each of the compression units CU1-CU4 may include 4×2 pixels, and the compression units CU1-CU4 may be horizontally or vertically adjacent in a picture. When the modified compression mechanism is activated, each of the compressors 115_1 and 115_2 may be configured to set a compression order according to a position of each pixel boundary between different pixel groups. For example, the compressor 118_1 compresses the compression unit CU1 prior to compressing the compression unit CU2, and the compressor 118_2 compresses the compression unit CU3 prior to compressing the compression unit CU4. In other words, two adjacent pixel sections located at the same pixel line are compressed in opposite compression orders. Since the modified compression scheme starts the compression from compression units near the pixel boundary between adjacent pixel groups, the bit budget allocation conditions near the pixel boundary may be more similar. In this way, the image quality around the pixel boundary in a reconstructed picture can be improved.

FIG. 8 is a flowchart illustrating another control and data flow of the data processing system shown in FIG. 1 according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 8. The exemplary control and data flow may be briefly summarized by following steps.

Step 802: Split pixel data of a plurality of pixels of one picture into a plurality of pixel data groups.

Step 804: Apply rate control to each of a plurality of compressors.

Step 806: Generate a plurality of compressed pixel data groups by using the compressors to compress the pixel data groups according to compression orders set based on pixel boundary positions.

Step 808: Pack/packetize the compressed pixel data groups into a plurality of output bitstreams, respectively.

Step 810: Transmit the output bitstreams via a plurality of display ports of a display interface, respectively.

Step 812: Receive an input bitstream from the display interface.

Step 814: Un-pack/un-packetize the input bitstream into a compressed data group.

Step 816: Generate a de-compressed pixel data group by using a de-compressor to de-compress the compressed pixel data group.

It should be noted that steps 802-810 are performed by the application processor (AP) 102, and steps 812-816 are performed by one of the driver ICs 104_1-104_N. As a person skilled in the art can readily understand details of each step shown in FIG. 8 after reading above paragraphs, further description is omitted here for brevity.

In above embodiments, the pixel data grouping setting DGSET defines selection of non-overlapped pixels for generating each pixel data group. In another pixel data grouping design, the pixel data grouping setting DGSET may define selection of overlapped pixels for generating each pixel data group. Hence, some pixels included in one pixel group are also included in another pixel group. Please refer to FIG. 9, which is a diagram illustrating a pixel data splitting operation performed by a mapper based on another pixel data grouping design. In this embodiment, based on the pixel data grouping setting DGSET that supports selection of overlapped pixels, the mapper 117 gathers pixel data of a pixel group as one pixel data group, where the pixel group includes all pixels belonging to one image partition and some pixels belonging to adjacent image partition(s). Hence, as shown in FIG. 9, the pixel data group D1 is composed of pixel data of a pixel group PG1 including all pixels belonging to the image partition A1 and pixel data of some pixels belonging to one adjacent image partition A2; the pixel data group D2 is composed of pixel data of a pixel group PG2 including all pixels belonging to the image partition A2 and pixel data of some pixels belonging to two adjacent image partitions A1 and A3; the pixel data group DN-1 is composed of pixel data of a pixel group PGN-1 including all pixels belonging to the image partition AN-1 and pixel data of some pixels belonging to two adjacent image partitions AN-1 and AN; and the pixel data group DN is composed of pixel data of a pixel group PGN including all pixels belonging to the image partition AN and pixel data of some pixels belonging to one adjacent image partition AN-1.

As can be seen in FIG. 9, two adjacent pixel groups have overlapped pixels, where the number of overlapped pixels may be programmable. In addition, concerning each of the pixel groups, the pixel group includes pixels inside an image partition to be displayed on a designated display region, and further includes pixels outside the image partition to be displayed on the designated display region. For example, the pixel group PG1 includes pixels of a portion of the image partition A2 that will not be displayed on the display region R1, the pixel group PG2 includes pixels of a portion of the image partition A1 and pixels of a portion of the image partition A3 that will not be displayed on the display region R2, the pixel group PGN-1 includes pixels of a portion of the image partition AN-2 and pixels of a portion of the image partition AN that will not be displayed on the display region RN-1, and the pixel group PGN includes pixels of a portion of the image partition AN-1 that will not be displayed on the display region RN.

The compressors 118_1-118_N compress the pixel data groups D1-DN corresponding to the pixel groups PG1-PGN having overlapped pixels, and accordingly generate the compressed pixel data groups D1′-DN′. In this embodiment, each of the pixel data groups D1-DN is compressed in the same compression order (e.g., an order from a left-most pixel in a pixel section of a pixel line to a right-most pixel in the same pixel section). The desired pixels (i.e., pixels needed to be displayed) in the pixel group are on one side of a pixel boundary, and additional pixels (i.e., overlapped pixels) in the pixel group are on the other side of the pixel boundary. Hence, the bit rate control applied to compression of the pixel group may lend the bit budget from the overlapped pixels to assign a larger bit budget to desired pixels near the pixel boundary. In this way, when reconstructed image partitions are displayed on the display regions R1-RN, the artifacts on the pixel boundaries can be reduced.

When the aforementioned pixel data grouping design that supports selection of overlapped pixels is employed by the application processor 102, the de-compressor 124 shown in FIG. 3 is configured to obtain a preliminary de-compressed pixel data group by de-compressing the compressed pixel data group un-packed from the input interface 122, and discards a portion of the preliminary de-compressed pixel data group that corresponds to pixels beyond a target display region (e.g., R1) to be driven by the driver IC (e.g., 104_1) to generate the de-compressed pixel data group (e.g., D1″).

FIG. 10 is a flowchart illustrating yet another control and data flow of the data processing system shown in FIG. 1 according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 10. The exemplary control and data flow may be briefly summarized by following steps.

Step 1002: Split a plurality of pixels of one picture into a plurality of pixel groups with overlapped pixels.

Step 1004: Apply rate control to each of a plurality of compressors.

Step 1006: Generate a plurality of compressed pixel data groups by using the compressors to compress a plurality of pixel data groups corresponding to the pixel groups.

Step 1008: Pack/packetize the compressed pixel data groups into a plurality of output bitstreams, respectively.

Step 1010: Transmit the output bitstreams via a plurality of display ports of a display interface, respectively.

Step 1012: Receive an input bitstream from the display interface.

Step 1014: Un-pack/un-packetize the input bitstream into a compressed data group.

Step 1016: Generate a preliminary de-compressed pixel data group by using a de-compressor to de-compress the compressed pixel data group.

Step 1018: Discard a portion of the preliminary de-compressed pixel data that corresponds to pixels beyond a target display region to be driven by the driver IC.

It should be noted that steps 1002-1010 are performed by the application processor (AP) 102, and steps 1012-1018 are performed by one of the driver ICs 104_1-104_N. As a person skilled in the art can readily understand details of each step shown in FIG. 10 after reading above paragraphs, further description is omitted here for brevity.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.