Title:
Method of patterning ultra-small structures
Kind Code:
A1


Abstract:
We describe a process to produce ultra-small structures of between ones of nanometers to hundreds of micrometers in size, in which the structures are compact, nonporous and exhibit smooth vertical surfaces. Such processing is accomplished with pulsed electroplating techniques using ultra-short pulses in a controlled and predictable manner.



Inventors:
Gorrell, Jonathan (Gainesville, FL, US)
Davidson, Mark (Florahome, FL, US)
Trucco, Andres (Gainesville, FL, US)
Tokarz, Jean (Hawthorne, FL, US)
Application Number:
11/203407
Publication Date:
02/15/2007
Filing Date:
08/15/2005
Assignee:
Virgin Islands Microsystems, Inc. (St. Thomas, VI, US)
Primary Class:
International Classes:
C25D5/02
View Patent Images:



Primary Examiner:
VAN, LUAN V
Attorney, Agent or Firm:
DAVIDSON BERQUIST JACKSON & GOWDEY LLP (McLean, VA, US)
Claims:
What is claimed is:

1. A method of patterning ultra-small structures on a surface, comprising: providing a conductive layer; depositing a mask layer on said conductive layer; defining a pattern in said mask layer; and growing said ultra-small structures on said surface in a pulse-electroplating process.

2. The method of claim 1 wherein said ultra-small structures are comprised of a material selected from the group consisting silver (Ag), copper (Cu), aluminum (Al), gold (Au) and platinum (Pt).

3. The method of claim 1 wherein said pulse-electroplating process comprises the step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one voltage pulse is between 1.5 and 12 volts, and each said at least one voltage pulse lasts for less than 1 microsecond.

4. The method of claim 3 wherein each said at least one voltage pulse is for a period of less than 500 ns.

5. The method of claim 3 further comprising: after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

6. The method of claim 5 wherein the rest period is between 1 microsecond and 500 ms.

7. The method of claim 1 wherein said mask layer is comprised of photoresist.

8. The method of claim 1 wherein said conductive layer is comprised of carbon.

9. The method of claim 1 wherein said conductive layer is comprised of metal.

10. The method of claim 1 wherein said conductive layer is comprised of a semiconducting material.

11. The method of claim 1 wherein said conductive layer is comprised of a transparent conductor such as indium tin oxide (ITO).

12. The method of claim 1 wherein said conductive layer is a conductive polymer.

13. The method of claim 1 wherein said conductive layer is a non-metallic conductor such as an ionic conductor, sodium chloride (NaCl).

14. The method of claim 3 wherein the series of voltage pulses includes at least one negative voltage pulse.

15. A method for patterning ultra-small features on a surface comprising: providing a conductive layer on said surface; depositing a layer of photoresist on said conductive layer; defining a pattern in said photoresist layer; and growing said ultra-small structures on said surface in a pulse-electroplating process.

16. The method of claim 15 wherein said conductive layer is comprised of carbon.

17. The method of claim 15 wherein said conductive layer is comprised of metal.

18. The method of claim 15 wherein said pulse-electroplating process includes a step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one voltage pulse lasts for less than 1 microsecond.

19. The method of claim 18 wherein each said at least one voltage pulse period is less than 500 ms.

20. The method of claim 18 wherein said pulse-electroplating process includes after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

21. The method of claim 18 wherein each said at least one voltage pulse is between 1.5 and 12 volts.

22. The method of claim 18 wherein the series of voltage pulses further comprises at least one negative voltage pulse.

23. A method for patterning ultra-small features on a surface comprising: providing a surface having a carbon layer thereon; depositing a mask layer on said carbon layer; defining a pattern in said mask layer; and growing said ultra-small structures on said surface in a pulse-electroplating process.

24. The method of claim 23 wherein said ultra-small structures are comprised of a material selected from the group consisting of silver (Ag), copper (Cu), aluminum (Al), gold (Au) and platinum (Pt).

25. The method of claim 23 wherein said pulse-electroplating process comprises the step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one voltage pulse is between 1.5 and 12 volts, and each said at least one voltage pulse lasts for less than 1 microsecond.

26. The method of claim 25 wherein each said at least one voltage pulse is for a period of less than 500 ns.

27. The method of claim 26 further comprising: after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

28. The method of claim 27 wherein said rest period is 1 microsecond to 500 ms.

29. The method of claim 23 wherein said mask layer is comprised of photoresist.

30. The method of claim 25, wherein the series of voltage pulses further comprises at least one negative voltage pulse.

31. A method for patterning ultra-small features on a surface comprising: providing said surface with a nickel (Ni) layer; depositing a silver (Ag) layer on said nickel layer; depositing a mask layer on said silver layer; defining a pattern in said mask layer; and growing said ultra-small structures on said surface in a pulse-electroplating process.

32. The method of claim 31 wherein said pulse-electroplating process comprises the step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one pulse is between 1.5 and 12 volts, and each said at least one pulse lasts for less than 1 microsecond.

33. The method of claim 31 further comprising: after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

34. The method of claim 33 wherein said rest period is 1 microsecond to 500 ms.

35. The method of claim 30 wherein said mask layer is comprised of photoresist.

36. The method of claim 32 wherein said series of voltage pulses further comprises at least one negative voltage pulse.

37. A method for patterning ultra-small features on a surface comprising: providing said surface with a nickel (Ni) layer; depositing a silver (Ag) layer on said nickel layer; depositing a mask layer on said silver layer; defining a pattern in said mask layer; and growing said ultra-small structures on said surface in a pulse-electroplating process that uses ultra-short pulses, wherein said pulse-electroplating process comprises the step of applying a series of voltage pulses comprising at least one ultra-short positive voltage pulse and at least one ultra-short negative voltage pulse, wherein each said at least one pulse is between 1.5 and 12 volts; and, after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

Description:

RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 10/917,571, filed on Aug. 13, 2004, entitled “Patterning Thin Metal Film by Dry Reactive Ion Etching,” which is commonly owned at the time of filing, and the entire contents of which is incorporated herein by reference.

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains material which is subject to copyright or mask work protection. The copyright or mask work owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright or mask work rights whatsoever.

FIELD OF THE DISCLOSURE

This disclosure relates to patterning ultra-small structures using pulsed electroplating.

INTRODUCTION

Electroplating is well known and is used in a variety of applications, including the production of microelectronics, For example, an integrated circuit can be electroplated with copper to fill structural recesses such as blind via structures.

In a basic electroplating procedure, samples are immersed in a suitable solution containing ions, typically cations, but anionic solutions are also known. An appropriate electrode is also immersed in the solution and a charge is applied that causes the deposition of metals ions from the solution onto the sample surface via an ionic reaction.

The current density, established by adjusting the electrode potential, controls the reaction rate at the sample surface. At high current density, the reaction rate becomes limited by diffusion of ions in the solution. Pulsed electroplating, also known as pulse plating, alters the current or voltage applied to the sample according to a predetermined waveform. The shape of the waveform pattern depends upon the required surface characteristics of the final plated structure.

Pulse plating can permit the use of simpler solutions containing fewer additives to achieve the plated surface. Pulse plating is well known as a method of improving coating density, ductility, hardness, electrical conductivity, wear resistance and roughness. In addition, pulse plating provides more uniform plating than other plating methods.

The production of compact, nonporous and smooth vertical surfaces is difficult with existing electroplating techniques. Porous structural morphologies produced in a controlled and predictable manner can also be advantageous to device designers.

Ultra-small structures encompass a range of structure sizes sometimes described as micro- or nano-sized. Objects with dimensions measured in ones, tens or hundreds of microns are described as micro-sized. Objects with dimensions measured in ones, tens or hundreds of nanometers or less are commonly designated nano-sized. Ultra-small hereinafter refers to structures and features ranging in size from hundreds of microns in size to ones of nanometers in size.

Catalysts, sensors, and filters represent a non-exhaustive list of examples of devices that can be fabricated or enhanced with structures of a porous morphology. The ability to create three-dimensional structures with a designed predictable structural morphology offers designers a method to realize new devices.

Ultra-small three-dimensional surface structures with sidewalls can be fabricated with coating techniques such as evaporation or sputtering. In both these techniques, a negative of the desired surface structures is created, usually using photolithographic techniques well known in the art. The patterned surface is then placed into a vacuum chamber and coated with the final material. After coating, the residual resist is removed.

However, with these techniques, patterned structures are known to cause a shadowing effect to occur during coating such that material deposition is uneven across the breadth of the patterned surface. In addition, the angles between the sidewalls created and the substrate surface often have angles other than the desired 90° orientation. The ability to create smooth, dense sidewalls oriented at a 90° angle relative to the substrate surface is desirable for the fabrication of a variety of ultra-small devices.

The ability to build significantly larger three-dimensional structures with smooth dense sidewalls employing the similar processing offers advantages to device designers. For example, smooth, dense sidewalls increase the efficiency of optical device function. It may also be beneficial in some microfluidic application.

Recent emphasis in the arts relates to the production of dense, smooth contiguous coatings using pulse-electroplating techniques. For example, in U.S. Patent Publication No. 20040231996A1, Web et al. describe a method of plating a copper layer onto a wafer with an integrated circuit including depressions using a pulse plating technique. In the preferred embodiment disclosed, the wafer is rotated during deposition. The rate of rotation affects the quality of layer produced. Depressions within the circuit layer are filled during the plating process.

Electroplating dendritic three-dimensional surface structures using electroplating techniques is also known. For example, U.S. Pat. No. 5,185,073, to Bindra et al., includes a description of forming dendritic surface structures using pulsed electroplating techniques. The structures produced are dense, but have angled sidewalls.

In 1995, Joo et al (“Air Cooling Of IC Chip With Novel Microchannels Monolithically Formed On Chip Front Surface,” Cooling and Thermal Design of Electronic Systems (HTD-Vol. 319 & EEP-Vol. 15), International Mechanical Engineering Congress and Exposition, San Francisco, Calif. November 1995, pp. 117-121) described fabricated cooling channels using direct current electroplate of nickel. The smoothness and microstructure of the walls created was not an issue. Direct current electro-plating processing tends to produce non-uniform structures across a die or wafer.

BRIEF DESCRIPTION OF FIGURES

The invention is better understood by reading the following detailed description with reference to the accompanying drawings in which:

FIG. 1 is a schematic of a typical apparatus.

FIGS. 2(a)-2(b) are plots of typical voltage waveform according to embodiments of the present invention.

FIG. 3 is an electron microscope photograph illustrating sample representative dense ultra-small structures.

FIG. 4 is an electron microscope photograph illustrating a sample representative structure with a varying morphology.

FIG. 5 is an electron microscope photograph illustrating a sample representative porous ultra-small structures.

FIGS. 6(a)-6(f) are electron microscope photographs illustrating various exemplary structures produced according to embodiments of the present invention.

FIGS. 7(a)-7(b) depict exemplary shapes and patterns made according to embodiments of the present invention.

DESCRIPTION OF PRESENTLY PREFERRED EXEMPLARY EMBODIMENTS OF THE INVENTION

FIG. 1 is a schematic drawing of a configuration of an example coating apparatus according to embodiments of the present invention. A computer such as personal computer 101 is connected to a function generator 102, e.g., by a standard cable such as USB cable 103. Personal computer 101 is also connected to analog input-output card 105, e.g., by standard USB cable 104.

Waveform functions on the personal computer 101 are drawn using a standard program included with function generator 102. After the personal computer 101 downloads the waveforms to function generator 102, the function generator sets characteristics such as amplitude, period, and offset of its output electrical signal. The output of function generator 102 is sent to the current amplifier 108 along cables 106 and 107. The cables 106 and 107 may be, e.g., standard USB cables.

In cases where the output current of the function generator is insufficient to carry out the plating, an amplifier 108 can be introduced between the function generation and the plating bath 112. Amplifier 108 increases the output current of the function generator 102, making it sufficient to carry out the plating without experiencing a voltage drop. Current amplifier 108 maintains an appropriately constant voltage in plating bath 112 as deposition occurs. Any DC voltage offset introduced by an imperfect amplifier can be corrected by programming an opposite DC offset from the function generator.

Time between pulses is controlled via a program that triggers the function generator output. This program is also used to start and stop the plating.

The output signal from the current amplifier 108 is provided to electrode switch 111 on cable 109. Analog input-output (I/O) card 105 sends a signal to electrode switch 111 via cable/line 114. Analog input-output card 105 is controlled by an output signal from the computer 101.

Electrode switch 111 generates an output signal that is sent to timer 116 (via cable 115). The signal output from timer 116 is connected to anode 117 in the plating bath 112. In currently preferred embodiments, the anode is a silver (Ag) metal plate, but there is no requirement that the anode consist of silver, and other materials, including (without limitation) copper (Cu), aluminum (Al), gold (Au) and platinum (Pt) may be used and are contemplated by the invention.

A second output signal is sent from current amplifier 108 via cable 110 (which may be, e.g., a USB cable) to sample 113 (which comprises the surface/substrate to be coated/plated by the metal on the anode 117). Sample 113 is the cathode. In presently preferred embodiments, substrates are rectangular and are about 1 cm by 2 cm. There is no requirement that the substrate be any minimum or maximum size.

An agitation mechanism such as agitation pump 118 is attached to plating bath 112. Agitation of the liquid in the bath 112 speeds up the deposition rate. The pump 118 agitates the solution, thereby moving the solution around the plating bath 112. The plating bath 112 is preferably large enough to permit even flow of the solution over the substrate.

The effect of agitation depends on the size and shape of the device being plated. In some cases, agitation reduces the plating time to thirty seconds on some of the smaller devices and down to ninety seconds on larger ones. Agitation also facilitates uniform thicknesses on all the devices across the substrate leading to higher yields. There are other known ways of agitation, including using an air pump to aerate the solution. For some applications, agitation may not be preferred at all.

An appropriate plating solution is placed into plating bath 112. In presently preferred embodiments, a silver plating solution is used. In the currently preferred embodiment the solution is Caswell's Silver Brush & Tank Plating Solution.

To ensure that the plating bath 112 is getting the desired period and amplitude, an oscilloscope 121 can be connected directly to the plating bath.

In one presently preferred embodiment, sample 113 is prepared by evaporating a 0.3 nanometer thick layer of nickel (Ni) onto the surface of a silicon (Si) wafer to form a conductive layer. The artisan will recognize that the substrate need not be silicon. The substrate in this example is substantially flat and may be either conductive or non-conductive with a conductive layer applied by other means. A 10 to 300 nanometer layer of silver (Ag) is deposited using electron beam evaporation on top of the nickel layer. Alternative methods of production can also be used to deposit the silver coating. The presence of the nickel layer improves the adherence of silver to the silicon. In an alternate embodiment, a thin carbon (C) layer may be evaporated onto the surface instead of the nickel layers. Alternatively, the conductive layer may comprise indium tin oxide (ITO) or comprise a conductive polymer.

The now-conductive substrate is coated with a layer of photoresist. In current embodiments, a layer of polymethylmethacrylate (PMMA) is deposited over top of the conductive coating. The PMMA may be diluted to produce a continuous layer of 200 nanometers. The photoresist layer is exposed with a scanning electron microscope (SEM) and developed to produce a pattern of the desired device structure. The patterned substrate is positioned in an electroplating bath 112. A range of alternate examples of photoresists, both negative and positive in type, exist that can be used to coat the conductive surface and then patterned to create the desired structure.

In the plating process, the voltage applied on the sample 113 is pulsed. FIGS. 2(a)-2(b) show a plot of a typical voltage waveform. In FIGS. 2(a)-2(b), the percentage of the total voltage applied on the sample is plotted versus time. In this waveform, a positive voltage pulse of between five and six volts is applied on the sample, and after some rest time, the voltage is reversed to a negative voltage. Plating occurs as the voltage applied on the substrate is negative-referenced to the counter electrode. It has been noticed that if the pulsed length is increased the plating pushes on the photoresist, creating slightly larger features.

During the intervals when the voltage is positive, material is removed from the structures. The optimum values of parameters such as peak voltage, pulse widths, and rest times will vary depending upon the size, shape and density of the devices on the substrate that are being plated, temperature and composition of the bath, and other specifications of the particular system to which this technique is applied.

FIG. 3 shows an image of a typical ultra-small feature fabricated using the example waveforms shown in FIGS. 2(a)-2(b). In the fabrication of these structures, the time between pulses was ten microseconds. The time between pulses can be varied to achieve a variety of structure morphologies.

After the devices are plated onto the surface, the conductive surface may be removed between the devices. Many methods of surface removal exist that can be applied in these circumstances. In one currently preferred exemplary surface removal method, if the ultra-small structures are comprised of silver, a thin layer of nickel is plated over the silver structures to mask them during a reactive ion etching process. A thin hard mask of other materials might also be used, including but not limited to a thin layer of silicon dioxide (SiO2) of silicon nitride (SiNx).

The reactive ion etching method is described in commonly-owned U.S. patent application Ser. No. 10/917,511 (Davidson, et al, filed Aug. 13, 2004), the entire contents of which are incorporated herein by reference. If the conductive layer consists of carbon, then the layer may be removed easily with oxygen. If the conductive surface is removed, the devices are insulated from each other. Material deposited over remaining photoresist is removed along with the photoresist using standard processing methods.

The desired characteristics of the ultra-small structures depend upon the application for which the structures are intended. Altering the nature of the voltage waveform can vary the characteristics of the ultra-small structures fabricated using this pulse-electroplating process.

For example, in the case of heat sinks, a very dense silver film contacting the substrate is required to draw the heat out of the chip. Then it might be better to have a less dense, larger surface area to conduct heat to the air or liquid cooling media. FIG. 4 shows an image of sample representative ultra-small structures with this desired morphology. In this alternative example, a negative voltage of two (2) volts was applied, with a time between pulses of fifty milliseconds. A wide range of morphologies can be achieved by altering parameters such as peak voltage, pulse widths, and rest times.

In some embodiments, a series of plating pulses including at least one positive voltage pulse and at least one negative voltage pulse, are applied. Preferably each voltage pulse is for an ultra-short period. As used herein, an “ultra-short period” is a period of less than one microsecond, preferably less than 500 ns, and more preferably less than or equal to 400 ns. Preferably there is a rest period between each of the pulses in the pulse series. In presently preferred embodiments of the invention, the series of plating pulses is repeated at least once, after an inter-series rest time. Preferably the inter-series rest time is 1 microsecond or greater. In some embodiments of the present invention, the inter-series rest time is between 1 microsecond and 500 ms. As used herein, the term “ultra-short voltage pulse” refers to a voltage pulse that lasts for an ultra-short period—i.e., a voltage pulse (positive or negative) that lasts less than one microsecond, preferably less than 500 ns, and more preferably less than or equal to 400 ns.

In some presently preferred implementations, the temperature used is 25° C. to 29° C., with 28° C. being preferable. In these preferred implementations, the distance from the cathode 113 to the anode 117 is 8 mm and a typical substrate size is about 1 cm×5 mm, ±2 mm.

Implementations of the current technique have been used to plate features 30 nm by 60 nm, up to 80 nm by 700 nm, with heights in the range 150 nm to 350 nm. Those skilled in the art will realize that as the shapes (areas) become smaller, plating time decreases. Pulses in these preferred implementations ranged from 1.5 microseconds to 400 nanoseconds, with the thinner pulses being used for the smallest features. In one implementation of the present invention, for larger structures, 500 nm by 1 micron and 350 nm high, longer pulses, on the order of 1.5 micron, were used.

Ultra-small porous structures may be fabricated as well. Such structures can be used, for example, as filters, sensors or gas separation media. FIG. 5 shows an image of sample representative of ultra-small structures having a porous structure. In this alternative example, a positive voltage pulse of between four and five volts is applied, and after some rest time, the voltage is reversed to a negative voltage.

FIGS. 6(a)-6(f) are electron microscope photographs illustrating various exemplary structures produced according to embodiments of the present invention.

FIGS. 7(a)-7(b) depict exemplary shapes and patterns made according to embodiments of the present invention. These shapes range from circular cavities to square cavities, as well as single and multiple cavities. Note that these drawings are not necessarily to scale.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.