TECHNICAL FIELD

[0001] The present invention relates to a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, a polishing body which is used in this CMP polishing apparatus, and a semiconductor device manufacturing method which uses this CMP polishing apparatus.

BACKGROUND TECHNOLOGY

[0002] As semiconductor integrated circuits have become finer and more highly integrated, the individual processes involved in semiconductor manufacturing processes have become more numerous and complicated. As a result, the surfaces of semiconductor devices are not always flat. The presence of step differences on the surfaces of semiconductor devices leads to step breakage of wiring and local increases in resistance, etc., and thus causes wiring interruptions and drops in electrical capacitance. In insulating films, furthermore, such step differences also lead to a deterioration in the withstand voltage and the occurrence of leaks.

[0003] Meanwhile, as semiconductor integrated circuits have become finer and more highly integrated, the wavelengths of light sources in semiconductor exposure apparatuses used in photolithography have become shorter, and the numerical aperture or so-called NA of the projection lenses used in such semiconductor exposure apparatuses has become larger. As a result, the focal depth of the projection lenses used in such semiconductor exposure apparatuses has become substantially shallower. In order to deal with such increasing shallowness of the focal depth, there is a demand for even greater planarization of the surfaces of semiconductor devices than that achieved so far.

[0004] To describe this in concrete terms, planarization techniques such as that shown in FIG. 9 have become essential in semiconductor manufacturing processes. FIG. 9 is a schematic diagram illustrating planarization techniques used in a semiconductor manufacturing process, and shows sectional views of a semiconductor device. In FIG. 9, 31 indicates a silicon wafer, 32 indicates an inter-layer insulating film consisting of S_iO₂, 33 indicates a metal film consisting of Cu, and 34 indicates the semiconductor device.

[0005] FIG. 9(a) shows an example of the planarization of an inter-layer insulating film 32 on the surface of the semiconductor device. FIG. 9(b) shows an example in which a so-called damascene is formed by polishing the metal film 33 on the surface of the semiconductor device. A chemical mechanical polishing or chemical mechanical planarization (hereafter referred to as “CMP”) technique is widely used as a method for planarizing the surfaces of such semiconductor devices. Currently, the CMP technique is the sole method that can be used to planarize the entire surface of a silicon wafer.

[0006] CMP was developed on the basis of silicon wafer mirror surface polishing methods, and is performed using a CMP apparatus of the type shown in FIG. 10. In FIG. 10, 35 indicates a polishing member, 36 indicates a member that holds the object of polishing (hereafter referred to as a “polishing head” in some instances), 37 indicates a silicon wafer which is the object of polishing, 38 indicates a polishing agent supply part, and 39 indicates a polishing agent. The polishing member 35 has a polishing pad 41 which is attached to the surface of a polishing platen 40. A sheet-form foam polyurethane is widely used as such a polishing pad 41.

[0007] The object of polishing 37 is held by the polishing head 36, so that it is caused to oscillate while being rotated, and is pressed against the polishing pad 41 of the polishing member 35 with a specified pressure. The polishing member 35 is also rotated, so that a relative motion is performed between the polishing member 35 and the object of polishing 37. In this state, the polishing agent 39 is supplied to the surface of the polishing pad 41 from the polishing agent supply part 38. The polishing agent 39 diffuses over the surface of the polishing pad 41, and enters the space between the polishing pad 41 and the object of polishing 37 as the polishing member 35 and object of polishing 37 move relative to each other, so that the surface of the object of polishing 37 that is to be polished is polished. Specifically, good polishing is accomplished by a synergistic effect of the mechanical polishing caused by the relative motion of the polishing member 35 and object of polishing 37 and the chemical action of the polishing agent 39.

[0008] Unlike the surfaces of wafers in a blank state, the surfaces of wafers that have semiconductor integrated circuits formed inside are not flat; in particular, there are usually step differences between portions in which chips are formed and portions in which chips are not formed. Accordingly, in cases where such wafers are polished, there is a need to eliminate local indentations and projections (this is called “local pattern planarity” while polishing the wafer in conformity to large periodic indentations and projections (undulations) of the wafer substrate itself, i.e., uniformly along such indentations and projections (undulations) (this is called “wafer global removal uniformity”).

[0009] In order to meet such demands, a method has been developed in which a polishing body is formed by pasting together a polishing pad and a soft pad, and this polishing body is used instead of the polishing pad 41 shown in FIG. 10. Specifically, as is shown in FIG. 11, a polishing body 44 is formed by pasting together a polishing pad 42 and a pad 43 which has a low elastic modulus and a large compressive deformation rate, and this polishing body 44 is attached to the polishing platen 40.

[0010] In such a state, when polishing of the type shown in FIG. 10 is performed, the pad 43 is caused to undergo compressive deformation by the force that is applied to the large undulation of the wafer 37 via the polishing pad 42, so that the polishing pad 42 also deforms in conformity to this deformation. Accordingly, polishing can be performed in which the amount of polishing is fixed in accordance with the undulation in the surface of the wafer 37. Meanwhile, in the case of local indentations and projections, the deformation of the polishing pad 42 is relatively small; accordingly, such indentations and projections can be removed by polishing.

[0011] In recent years, the degree of integration of semiconductor integrated circuits has become increasingly higher; as a result, a wiring rule of 0.1 μm or less has begun to be used. Furthermore, demand for the polishing of system LSIs has increased, and in system LSIs, the distribution of pattern density has become severe. In cases where wafers are polished which thus have patterns determined by a fine wiring rule or patterns with a severe density distribution formed inside, it is difficult to satisfy both the requirements of “wafer global removal uniformity” and the requirements of “local pattern planarity” even if a polishing body of the above-mentioned type is used. Specifically, in the case of such wafers, local indentations and projections tend to be large; accordingly, as a result of the accompanying compressive deformation of the pad 43 and the deformation of polishing pad 42 in conformity to this deformation of the pad 43, it is difficult to ensure “local pattern planarity.”

DISCLOSURE OF THE INVENTION

[0012] The present invention was devised in order to solve such problems. The object of the present invention is to provide a polishing body which can satisfy both the requirements of “wafer global removal uniformity” and the requirements of “local pattern planarity” even in cases where wafers are polished which have patterns that use a wiring rule of 0.1 μm or less or patterns that have a severe density distribution are formed inside, a CMP polishing apparatus using this polishing body, and a semiconductor device manufacturing method using such a CMP apparatus.

[0013] The first invention of the present application which is used to achieve the above-mentioned object is a polishing body for a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, wherein a polishing pad, a hard elastic member and a soft member are laminated in that order, and the above-mentioned hard elastic member is constructed so that the amount of deformation of this member at the polishing load that is applied during polishing is smaller than the step difference permitted in the above-mentioned wafer in an interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits, and is greater than the TTV permitted in the above-mentioned wafer in the interval corresponding to one chip.

[0014] Here, the term “TTV (total thickness variation)” refers to the indentations and projections in the wafer as a whole. The interval corresponding to the maximum pattern of the semiconductor integrated circuits and the interval corresponding to one chip are shown in FIG. 1.

[0015] FIG. 1(a) shows a sectional view of the wafer prior to polishing. In this figure, 1 indicates the wafer substrate, 2 indicates patterns consisting of circuits and wiring, etc., and 3 indicates an inter-layer insulating layer. The patterns 2 consisting of circuits and wiring are formed on the surface of the substrate 1, and the inter-layer insulating layer 3 is formed on top of this, so that the patterns 2 consisting of circuits and wiring are insulated from each other. The interval corresponding to the maximum pattern of the semiconductor integrated circuits refers to the interval corresponding to the distance a of the recessed part of the inter-layer insulating film 3 that covers the patterns 2 of circuits and wiring that are most separated from each other within one chip. Currently, the interval corresponding to the maximum pattern of such semiconductor integrated circuits is approximately 4 mm.

[0016] FIG. 1(b) shows a single wafer, with a plurality of chips 5 being formed on this wafer 1. The interval corresponding to one chip refers to the interval corresponding to one side b in a case where the shape of the chip is square. Currently, this interval is approximately 20 mm. In cases where the shape of the chip is not square, or in cases where chips of different dimensions are formed on one wafer, this interval refers to the distance corresponding to the largest side.

[0017] Furthermore, the hard elastic member refers to an elastic member with a Young's modulus of 10,000 Kg/mm² or greater; metal members may be cited as typical examples. The soft member refers to a member that has a compression rate of 10% or greater when a pressure of 1 Kg/cm² is applied; chloroprene rubber members containing air bubbles, or elastic nonwoven fabrics, may be cited as typical examples.

[0018] In the present means, a hard elastic member is sandwiched between the polishing pad and a soft member. Furthermore, the amount of deformation of this hard elastic member at the load that is applied during polishing is set so that this amount of deformation is smaller than the step difference that is permitted in the above-mentioned wafer in the interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits. Accordingly, since the hard elastic member is not subjected to deformation exceeding the permitted step difference in the interval corresponding to the maximum pattern, “local pattern planarity” is ensured.

[0019] Meanwhile, the amount of deformation of the hard elastic member at the polishing load that is applied during polishing is set so that this amount of deformation is greater than the TTV permitted in the wafer in the interval corresponding to one chip. Accordingly, the hard elastic member can deform in conformity to the step difference over the distance corresponding to one chip, and the polishing pad also shows a corresponding deformation in conformity to these step differences, so that a uniform amount of polishing can be performed in accordance with these step differences. Consequently, “wafer global removal uniformity” is ensured.

[0020] The second invention of the present application that is used to achieve the above-mentioned object is the polishing body of the first invention, wherein the above-mentioned hard elastic member is constructed from a metal plate that will not dissolve in the polishing agent.

[0021] In the above-mentioned first invention, there are no particular stipulations regarding the material of the above-described hard elastic member. Accordingly, a hard plastic or hard rubber, for example, can be used. However, a hard plastic or hard rubber, etc., has a small Young's modulus; accordingly, if such a material is used in the above-described first invention, the thickness of the member must be set at a large value. If this thickness is increased, the degree of parallel orientation of the two surfaces deteriorates; furthermore, irregularities in thermal expansion occur as a result of temperature irregularities caused by the heat generated during polishing, and such irregularities cause a deterioration in planarity.

[0022] In the present invention, since the above-described hard elastic member is formed from a metal, the Young's modulus of the hard elastic member is high; accordingly, the thickness of this member can be reduced. Consequently, the degree of parallel orientation of the two surfaces can be maintained at a favorable value, and irregularities in thermal expansion can be reduced, so that the planarity can be maintained at a favorable value. Furthermore, the reason that the type of metal used is limited to a metal that will not dissolve in the polishing agent is as follows: specifically, if the metal dissolves in the polishing agent, there may be cases in which this has a deleterious effect on the semiconductor integrated circuits that are formed on the wafer. Stainless steel and titanium may be cited as examples of metals that will not dissolve in commonly used polishing agents.

[0023] The third invention of the present application that is used to achieve the above-mentioned object is the polishing body of the above-mentioned second invention, wherein the above-mentioned metal plate is a stainless steel plate, and the thickness h of this plate is such that 0.1 mm<h<0.94 mm.

[0024] In the present means, in the case of a commonly polished wafer, the effect described in the above-mentioned first means can be obtained; furthermore, the effect described in the above-mentioned second means can also be obtained. In addition, a stainless steel plate is readily available, and is less expensive than other materials.

[0025] As will be described in the working configurations later, in cases where it is assumed that the permitted step difference at a wiring rule of 0.35 μm is 0.35 μm and that the TTV is 5 μm, it is assumed that the permitted step difference at a wiring rule of 0.10 μm is 0.10 μm and that the TTV is 2 μm, and it is assumed that the interval corresponding to the maximum pattern of the semiconductor integrated circuits is 4 mm and that the interval corresponding to one chip is 20 mm, a stainless steel thickness h which is such that 0.1 mm<h<0.94 mm satisfies the conditions fixed by the above-mentioned first invention at a surface pressure of 100 g/cm² to 700 g/cm². Accordingly, in the present invention, the thickness of the stainless steel is limited as described above.

[0026] The fourth invention of the present application that is used to achieve the above-mentioned object is a polishing body for a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, wherein a polishing pad, a hard elastic member and a soft member are laminated in that order, and these parts are constructed so that the combined amount of deformation of the polishing pad, hard elastic member and soft member at the polishing load that is applied during polishing is smaller than the height of the indentations and projections of the above-mentioned maximum pattern in the interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits, and is greater than five times the TTV that is permitted in the above-mentioned wafer.

[0027] The term “height of the indentations and projections of the maximum pattern” refers to the depth of the recessed part corresponding to portion a in FIG. 1(a).

[0028] In the present means, a hard elastic member is sandwiched between the polishing pad and a soft member. Furthermore, the combined amount of deformation of the polishing pad, hard elastic member and soft member at the polishing load that is applied during polishing is smaller than the height of the indentations and projections of the above-mentioned maximum pattern in the interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits. Accordingly, since the polishing body is not subjected to deformation exceeding the height of the indentations and projections of the maximum pattern in the interval corresponding to the maximum pattern, the step difference between patterns following polishing can be suppressed to a difference that is less than the height of the indentations and projections of the maximum pattern. Consequently, “local pattern planarity” is ensured.

[0029] Meanwhile, the combined amount of deformation of the polishing pad, hard elastic member and soft member at the polishing load that is applied during polishing is set so that this amount of deformation is greater than five times the TTV that is permitted in the wafer in the interval corresponding to one chip. Generally, it is known that the amount of deformation of the polishing body must be five times the required TTV or greater if “wafer global removal uniformity” is to be obtained. Accordingly, as a result of the combined amount of deformation of the polishing pad, hard elastic member and soft member being set so that this amount of deformation is greater than five times the TTV that is permitted in the wafer in the interval corresponding to one chip, the polishing pad also deforms in conformity to the step differences in cases where there are step differences in the distance corresponding to one chip. Accordingly, a uniform amount of polishing can be performed in accordance with these step differences. Consequently, “wafer global removal uniformity” is ensured.

[0030] The fifth invention of the present application that is used to achieve the above-mentioned object is the polishing body of the above-mentioned fourth invention, wherein the above-mentioned hard elastic member is constructed from a metal plate that will not dissolve in the polishing agent.

[0031] In the above-mentioned fourth invention, there are no particular stipulations regarding the material of the above-mentioned hard elastic member. Accordingly, a hard plastic or hard rubber, for example, can be used. However, since hard plastics and hard rubbers, etc., have a small Young's modulus, the thickness must be increased if such materials are used in the above-mentioned fourth means. When the thickness increases, the degree of parallel orientation of the two surfaces deteriorates; furthermore, irregularities in thermal expansion occur as a result of temperature irregularities caused by the heat generated during polishing, and such irregularities cause a deterioration in planarity.

[0032] In the present invention, since a metal is used as the material of the above-mentioned hard elastic member, the Young's modulus is high; accordingly, the thickness of the member can be reduced. Consequently, the degree of parallel orientation of the two surfaces can be maintained at a favorable value, and irregularities in thermal expansion can also be reduced, so that the planarity can be maintained at a favorable value. Moreover, the reason that the type of metal used is limited to a metal that will not dissolve in the polishing agent is as follows: specifically, if the metal dissolves in the polishing agent, there are cases in which this has a deleterious effect on the semiconductor integrated circuits that are formed on the wafer. Examples of metals that will not dissolve in commonly used polishing agents include stainless steel and titanium.

[0033] The sixth invention of the present application that is used to achieve the above-mentioned object is the polishing body of the fifth invention, wherein the above-mentioned polishing pad consists of a urethane foam material, the above-mentioned metal plate is a stainless steel plate, the thickness of the above-mentioned polishing pad is 0.1 to 3 mm, the thickness of the above-mentioned metal body is 0.05 to 0.6 mm, and the thickness of the above-mentioned soft member is 0.5 to 2.5 mm.

[0034] A urethane foam material is superior as the material of a polishing pad; furthermore, a stainless steel plate is easy to obtain, and is less expensive than other materials. In cases where such materials are used, as will be described in the embodiments later, the requirements of both “wafer global removal uniformity” and “local pattern planarity” can be satisfied under advantageous conditions by setting the thicknesses of the polishing pad, metal plate and soft member as described above.

[0035] If the thickness of the polishing pad is less than 0.1 mm, the grooves used to conduct the slurry, which are ordinarily formed in the polishing pad, are eliminated.

[0036] Accordingly, in the present means, the thickness of the polishing pad is limited to a thickness of 0.1 mm or greater. Furthermore, even if the thickness of the polishing pad exceeds 3 mm, no particular advantage is gained, and there is no great difference between such a polishing body and a polishing body in which no metal plate is sandwiched between the other parts as described above; accordingly, in the present means, the thickness of the polishing pad is limited to a thickness of 3 mm or less.

[0037] In cases where the thickness of the metal body is less than 0.05 mm, “local pattern planarity” deteriorates as the thickness of the polishing pad is reduced, so that there is no great difference between such a polishing body and a polishing body in which no metal plate is sandwiched between the other parts as described above. Accordingly, in the present means, the thickness of the metal body is limited to a thickness of 0.05 mm or greater. On the other hand, if the thickness of the metal body exceeds 0.6 mm, the limiting conditions of the above-mentioned fourth invention cannot be realized in the case of a wafer with a TTV of 1 μm; accordingly, in the present means, the thickness of the metal body is limited to a thickness of 0.6 mm or less.

[0038] Since the soft member is on the back surface of the metal body, the thickness of the soft member does not greatly affect the “wafer global removal uniformity” or “local pattern planarity.” However, since an experiment (simulation) for the purpose of deriving the limits on the above-mentioned respective numerical values in the present invention was conducted in the range of 0.5 to 2.5 mm, the thickness is limited to this range.

[0039] The seventh invention of the present application that is used to achieve the above-mentioned object is the polishing body of any of the above-mentioned first through sixth inventions, wherein the above-mentioned soft member has a torsional strength which is such that this member is not damaged when the member rotates with a load applied during polishing.

[0040] In the present invention, the above-mentioned soft member has a torsional strength which is such that this member is not damaged when the member rotates with a load applied during polishing; accordingly, polishing can be performed smoothly.

[0041] The eighth invention of the present application that is used to achieve the above-mentioned object is the polishing body of any of the above-mentioned first through seventh inventions, wherein the above-mentioned hard elastic member and soft member are fastened by bonding, and the above-mentioned hard elastic member and polishing pad are fastened by vacuum suction.

[0042] In the present invention, since the hard elastic member and polishing pad are fastened by vacuum suction, the polishing pad can easily be replaced when the polishing pad becomes worn.

[0043] The ninth invention of the present application that is used to achieve the above-mentioned object is the polishing body of any of the above-mentioned first through seventh inventions, wherein the above-mentioned hard elastic member and soft member are fastened by bonding means with a strong peeling strength, and the above-mentioned hard elastic member and polishing pad are fastened by bonding means with a weak peeling strength.

[0044] In the present invention, since the above-mentioned hard elastic member and soft member are fastened by bonding means (adhesive agent or two-sided tape, etc.) with a strong peeling strength, and the above-mentioned hard elastic member and polishing pad are fastened by bonding means (adhesive agent or two-sided tape, etc.) with a weak peeling strength, the polishing pad can be peeled from the hard elastic member in a state in which the hard elastic member and soft member remain bonded. Accordingly, the polishing pad can easily be replaced when the polishing pad becomes worn.

[0045] The tenth invention of the present application that is used to achieve the above-mentioned object is a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, and which has the polishing body of any of the above-mentioned first through ninth inventions.

[0046] In the present invention, since the polishing body of one of the above-mentioned first through ninth inventions is used, the effects described in the descriptions of the respective polishing bodies can be obtained.

[0047] The eleventh invention of the present application that is used to achieve the above-mentioned object is a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, and which has the polishing body of the above-mentioned eighth or ninth invention, wherein the dimensions of the above-mentioned polishing pad are set so that these dimensions are smaller than the dimensions of the wafer that is being polished.

[0048] There are two types of CMP polishing apparatuses, i.e., apparatuses in which the dimensions of the polishing pad are larger than the dimensions of the wafer that is being polished, and apparatuses in which the dimensions of the polishing pad are smaller than the dimensions of the wafer that is being polished. In the present invention, the polishing body of the above-mentioned eighth or ninth invention is used in the latter type of apparatus. Accordingly, since the size of the polishing body pad is small, attachment by vacuum suction can easily be accomplished, so that the polishing pad can be securely fastened to the hard elastic member. Furthermore, in such a CMP apparatus, since the polishing pad is small, frequent replacement of the polishing pad is necessary. Accordingly, an especially great effect is obtained by using the polishing body of the above-mentioned eighth or ninth invention, in which replacement of the polishing pad is easy.

[0049] The twelfth invention of the present application that is used to achieve the above-mentioned object is a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, and which has the polishing body of the above-mentioned seventh invention, wherein the dimensions of the above-mentioned polishing pad are set so that these dimensions are smaller than the dimensions of the wafer that is being polished, and the permissible shear stress of the above-mentioned soft member is greater than 0.5 Kg/cm².

[0050] According to findings obtained by the present inventors, in the case of a CMP polishing apparatus in which the dimensions of the polishing pad are set so that these dimensions are smaller than the dimensions of the wafer that is being polished, the above-mentioned soft member can be endowed with a torsional strength which is such the member is not damaged when the member rotates with a load applied during polishing, by setting the permissible shear stress of the above-mentioned soft member at a value that is greater than 0.5 Kg/cm².

[0051] The thirteenth invention of the present application that is used to achieve the above-mentioned object is a semiconductor device manufacturing method which is characterized in that this method has a process in which the polishing of wafers is performed using the CMP polishing apparatus of any of the abovementioned tenth through twelfth inventions.

[0052] In the present invention, wafers can be polished while satisfying the requirements of both “wafer global removal uniformity” and “local pattern planarity,” which are required in the polishing of wafers that have semiconductor devices formed inside. Accordingly, a semiconductor exposure apparatus which has a shallow focal depth can be used, and semiconductor devices that have fine patterns can be manufactured with a good yield.