DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Embodiments of the present invention will be described in detail with reference to the drawings.

[0028] FIG. 1 is a circuit structural view showing an MRAM of an embodiment of the present invention.

[0029] The MRAM of this embodiment includes memory cells C11, C12, C13, C14, C21, C22, C23, C24, C31, C32, C33, C34, C41, C42, C43, C44, arranged in a 4×4 matrix state writing lines WL1, WL2, WL3, WL4, bit lines BL1, BL2, BL3, BL4, field effect transistors Ts1, Ts2, Ts3, Ts4, field effect transistors Ts1′, Ts2′, Ts3′, Ts4′, field effect transistors Tb1, Tb2, Tb3, Tb4, sense amplifiers SA1, SA2, SA3, SA4, and word lines WDL1 to WDL4.

[0030] The bit lines BL1, BL2, BL3, BL4 are arranged in parallel with each other, and the writing lines WL1, WL2, WL3, WL4 are parallel with each other and are arranged to intersect with the bit lines BL1, BL2, BL3, BL4.

[0031] The memory cell C1 includes a memory element selecting field effect transistor T11 and a memory element R11 functioning as a variable resistor in which an electric resistance value can be changed by selecting a magnetization direction of a magnetic substance. As the memory element, although any element may be used as long as a magneto-resistance effect can be obtained, a TMR (Tunnel Magneto-Resistance) element having such a structure that an insulating layer is sandwiched between magnetic layers, is particularly preferable since an MR ratio is large. Besides, a drain of the field effect transistor T11 is connected with one terminal of the TMR element R11, and a source of the field effect transistor T11 is grounded.

[0032] The other memory cells have the same structure.

[0033] The gates of the field effect transistors T11, T21, T31, T41; T12, T22, T32, T42; T13, T23, T33, T43; T14, T24, T34, T44 are connected to the common word lines. These are provided particularly to select a specified memory element to carry out reproducing at the time of information regeneration. The word line is a wiring for turning on and off the field effect transistor by applying a predetermined voltage to the gate.

[0034] Besides, the other terminal of the TMR element is connected to the bit line BL1. The field effect transistors Ts1, Ts2, Ts3, Ts4, Ts1′, Ts2′, Ts3′, Ts4′ are such switching elements that when they are turned on, the voltage levels of the bit lines BL1, BL2, BL3, BL4 are inputted to input terminal of the corresponding sense amplifiers SA1, SA2, SA3, SA4.

[0035] The sense amplifiers SA1, SA2, SA3, SA4 are signal detection circuits which output “1” or “0” according to the result of a comparison between the levels of two input voltages.

[0036] The field effect transistors Tb1, Tb2, Tb3, Tb4 are such switching elements that they are turned on when writing currents are made to flow to the corresponding bit lines, and ground the respective bit lines to cause the writing currents to flow.

[0037] The writing of information in the MRAM shown in FIG. 1 is carried out by causing currents to flow to both a desired bit line and writing line. Besides, the readout of information is carried out in such a manner that two field effect transistors (for example, Ts1 and Ts1′) connected to one sense amplifier (for example, SA1) are successively turned on, and a voltage variation at that time is detected by the sense amplifier.

[0038] These circuits are formed on a semiconductor substrate.

[0039] FIGS. 2A and 2B are views schematically showing magnetization states of magneto-resistance effect elements used as memory elements. FIG. 2A shows a horizontal magnetization film, and FIG. 2B shows a vertical magnetization film. The horizontal magnetization means that magnetization occurs in a film plane, and the vertical magnetization means that magnetization occurs perpendicularly to the film plane. In either case, the magnetization of a magnetic film is inverted by a magnetic field induced by a current flowing to a wiring. In this embodiment, although either of the horizontal magnetization and the vertical magnetization may be used, for the purpose of achieving high memory density, it is especially preferable to use the vertical magnetization film since the memory element can be easily made small.

[0040] In either case of the horizontal magnetization (FIG. 2A) and the vertical magnetization (FIG. 2B), the memory element has such a structure that a non-magnetic film 17 such as a tunnel insulating film is sandwiched between a magnetic material film (hard layer) 16 having high coercive force and a magnetic material film (soft layer) 16′ having coercive force lower than the former. A flowing tunnel current is different between a case where the magnetization directions of the two magnetic films 16, 16′ are in parallel with each other and in the same direction (hereinafter referred to as parallel) and a case where they are in parallel with each other and in the opposite direction (hereinafter referred to as anti-parallel), and the resistance value of the memory element is different. Note that, instead of the tunnel insulating film 17, a conductive layer may be naturally used to form a GMR element.

[0041] The change of the magnetization at the time when an external magnetic field is applied to the hard layer 16 and the soft layer 16′ draws a hysteresis curve as shown in FIG. 3. For example, in the case where magnetization given from the outside to the magnetic film magnetized in a negative direction (lower part in FIG. 3) is gradually increased, when it exceeds a predetermined magnetic field intensity Hc, magnetization in a positive direction starts, and when it reaches a predetermined magnitude, the magnetization is saturated. Since the magnetic films 16 and 16′ are different in coercive force, they are different from each other in magnetic field intensity at which the magnetization starts and in magnetic field intensity at which the magnetization is saturated. The magnetic field intensity at which the magnetization of the magnetic film 16 having high coercive force starts is higher than the magnetic field intensity at which the magnetization of the magnetic film 16′ having low coercive force is saturated.

[0042] For example, as a layer for holding information, the hard layer 16 having high coercive force is used. When stored information is rewritten, the magnetization direction of the hard layer 16 is changed. Thus, a relatively large external magnetic field is required to rewrite the information. In this embodiment, writing currents are made to flow to both the writing line (WL) and the bit line (BL) to select a specified memory element by a resultant magnetic field at the intersection, and the magnetization direction of the hard layer 16 is determined. According to the structure of the embodiment, the soft layer 16′ may be such that its coercive force is low and information can not be ensured for a long time, and the magnetization can be inverted by applying a relatively low external magnetic field at a readout operation. The magnetic layers are adjusted so that even if the magnetization of the soft layer 16′ is inverted at the time of readout, the magnetization of the hard layer 16 is not inverted. Besides, information may be naturally recorded by the magnetization direction of the soft layer while the magnetization of the hard layer is fixed.

[0043] As a material of the memory element, a metal material, an alloy, or the like is used for the magnetic film of the hard layer 16 and the soft layer 16′ , and an oxide insulating material such as Al2O3 is often used for the tunnel insulating film 17.

[0044] A memory chip in this embodiment is constructed using the foregoing memory cell.

[0045] FIG. 4 shows a memory cell array in a memory chip including the foregoing memory cell. Each of memory cell arrays CA1 to CA32 includes 256 memory cells connected to one bit line. Each of units is constituted by the 32 memory cell arrays CA1 to CA32. Accordingly, one unit includes the memory cells of about 8 kilobits, and a current pulse is simultaneously applied to a group of 32 sense amplifiers to start them at once, so that information of 32 bits can be parallel read out by one operation. Further, as shown in FIG. 5, by the use of the unit having the recording capacity of 8 kilobits, a memory chip of about 64 kilobits is constituted by eight units U1 to U8. When the division of memory cells is changed in FIGS. 4 and 5, each of the units U1 to U8 may be regarded as including 256 memory cell groups each composed of 32 memory cells.

[0046] Next, a process of reading out information from such an MRAM will be described. Here, as an example, a memory cell array including four sense amplifiers is used, and a case where parallel readout is carried out from a plurality of memory cell arrays in a unit will be described with reference to FIGS. 6 to 9. Although FIGS. 6 to 9 exemplify a horizontal magnetization matrix cell of 4×4 bits, also in the foregoing unit including the matrix cell of 256×32 bits, parallel readout can be carried out by the same method.

[0047] Here, a case where information stored in memory elements R13, R23, R33, R43 are parallel read out will be described as an example.

[0048] First, as shown in FIG. 6, a pulse current in an arrow direction is made to flow to only a writing line WL3 to generate magnetization facing the right in FIG. 6 in soft layers of the TMR elements R13, R23, R33, R43. By this, in a cell in which the magnetization of the hard layer faces the right, the magnetization of the hard layer and that of the soft layer become parallel to each other, and a low resistance state occurs. Besides, in a cell in which the magnetization of the hard layer faces the left, the magnetization of the hard layer and that of the soft layer become anti-parallel to each other, and a high resistance state occurs.

[0049] Next, as shown in FIG. 7, in a state where the field effect transistors T13, T23, T33, T43 are turned on by applying a predetermined voltage to a word line, constant currents are made to flow to bit lines BL1, BL2, BL3, BL4, and further, field effect transistors Ts1, Ts2, Ts3, Ts4 are turned on, so that the respective potentials of the bit lines BL1, BL2, BL3, BL4 are inputted to the plus side terminals of sense amplifiers SA1, SA2, SA3, SA4.

[0050] Next, as shown in FIG. 8, a pulse current in an arrow direction is made to flow to only the writing line WL3, and magnetization opposite to that of FIG. 6 is generated in the soft layer of the TMR elements R13, R23, R33, R43. By this, in the cell in which the magnetization of the hard layer faces the right, the magnetization of the hard layer and that of the soft layer become anti-parallel to each other, and the high resistance state occurs. Besides, in the cell in which the magnetization of the hard layer faces the left, the magnetization of the hard layer and that of the soft layer become parallel to each other, and the low resistance state occurs.

[0051] Next, as shown in FIG. 9, constant currents are made to flow to the bit lines BL1, BL2, BL3, BL4 in a state where the TMR elements T13, T23, T33, T43 are turned on, and further, the field effect transistors Ts1′, Ts2′, Ts3′, Ts4′ are turned on, so that the respective potentials of the bit lines BL1, BL2, BL3, BL4 are inputted to the minus side terminals of the sense amplifiers SA1, SA2, SA3, SA4.

[0052] As a result, among the respective bit lines BL1, BL2, BL3, BL4, the sense amplifier arranged at one connected with the hard layer having the magnetization facing the left outputs a “High” level signal. Besides, the sense amplifier arranged at one connected with the hard layer having the magnetization facing the right outputs a “Low” level signal. For example, when it is assumed that the magnetization direction of the hard layer faces the right in the TMR elements R13 and R33, and the magnetization direction of the hard layer faces the left in the TMR elements R23 and R43, the sense amplifiers SA1 and SA3 output the “High” level signal, and the sense amplifiers SA2 and SA4 output the “Low” level signal.

[0053] FIG. 10 is a timing chart showing the operation states of the respective wirings and FETs in the readout method of FIGS. 6 to 9. According to FIG. 10, it is understood that information of four bits is parallel outputted in a time of eight clock pulses.

[0054] FIG. 11 is an explanatory view for explaining a readout method of information stored in a memory chip in which eight units each having 256×32 memory cells are disposed.

[0055] In each of the units U1, U2, U3, U4, U5, U6, U7, U8, a desired memory cell group is selected by a similar method to that shown in FIGS. 6 to 9, and when 32 sense amplifiers are activated at the same time, data of 32 bits are outputted in parallel.

[0056] Each of the units U1, U2, U3, U4, U5, U6, U7, U8 includes 256 memory cell groups. Here, attention is given to four memory cell groups of each unit, which are shown in FIG. 11.

[0057] First, access to 32 memory cells of a memory cell group U1a is started by a clock of a first pulse. The access to the memory cell group 1a is carried out similarly to that shown in FIG. 10, and information is outputted by a clock of an eighth pulse.

[0058] Next, access to 32 memory cells of a memory cell group U2a is started by a clock of a second pulse. The access to the memory cell group U2a is also carried out similarly to that shown in FIG. 10, and information is outputted by a clock of a ninth pulse.

[0059] Hereinafter, in the same manner, access to a memory cell group U3a is started by a clock of a third pulse, and an access to a memory cell group U4a is started by a clock of a fourth pulse. Besides, when access is started up to a memory cell group U8a, next, access to a memory cell group U1b is started.

[0060] Accordingly, information of 32 bits is outputted.every clock subsequent to an eighth pulse. For example, if the readout of the MRAM is carried out by the readout method of this embodiment at a clock frequency of 66 MHz, first 32-bit data is outputted after 120 nsec from the start of the first access, and then, 32-bit data is outputted every 15 nsec.

[0061] A memory array set including the matrix type memory cells, the sense amplifiers, and the like is called a unit, and a memory chip is constituted by a plurality of units (for example, eight units).

[0062] Besides, in general, a clock pulse of a predetermined frequency is used to drive a memory element, and the timing of voltage application, the start of the sense amplifier, and the like are synchronized. As an example, in this embodiment, the description has been made under a clock frequency of 66 MHz (that is, frequency of 15 ns.).

[0063] As described above, in the present invention, the sense amplifiers of the units are successively activated (for example, up to eight units) in such a manner that a plurality of sense amplifiers (for example, 32 sense amplifiers) in a certain unit are activated in synchronization with a clock pulse so that information in the unit is read out at the same time, a plurality of sense amplifiers in another unit are activated in synchronization with a next clock pulse so that information in the unit is read out at the same time, and subsequently, a plurality of sense amplifiers in still another unit are activated in synchronization with a further next clock pulse.

[0064] The sense amplifiers of the first unit completes the output of the information until the eighth pulse of the clock, and can start the next readout operation from the ninth clock pulse of the clock. By this operation, the information (32 bits) of the 32 sense amplifiers can be outputted per clock pulse, and further, information is successively outputted every clock pulse.

[0065] If the readout method of this embodiment is applied to a driving method in which the magnetization direction of the soft layer 16′ is inverted to change the electric resistance value of the variable resistor, and information is read out from a difference between potentials before and after the inversion, the information of the MRAM can be read out at an information readout speed comparable to a synchronous DRAM. This is one of great features of the present invention.

[0066] Further, a capacitor charged by a potential of a bit line at a readout operation may be provided between the input terminal of the sense amplifier and the ground potential. In the sense amplifier, since the potential of one input terminal is held as a reference value by the capacitor, after the magnetization direction of the soft layer 16′ is inverted, the potential given to the other input terminal is compared with the reference value.

[0067] Note that, a circuit for generating a predetermined reference value as a voltage signal is provided, and the voltage signal of the reference value generated by the circuit may be inputted to the other input terminal of the sense amplifier. This case is shown in FIG. 12. In this case, the sense amplifier compares the voltage level of the one input terminal, that is, the voltage level of the bit line with the voltage level of the other input terminal, that is, the reference value. Note that, in this case, as the circuit for generating the predetermined reference value, a reference cell having the same structure as the memory cell may be used, or a circuit in which memory elements of a high resistance state and a low resistance state are parallel connected may be used. Of course, a power supply circuit for generating a voltage may be separately provided.

[0068] Next, specific examples of the MRAM of this embodiment will be described.

First Specific Example

[0069] In a first specific example, a description will be given of a case where a TMR element having such a structure that a tunnel insulating film is sandwiched between two magnetic thin films is used as a memory element.

[0070] Here, the memory element has the structure in which the tunnel insulating film is sandwiched between the hard layer having high coercive force and the soft layer having coercive force lower than the former, and as shown in FIG. 2A, the horizontal magnetization is caused. Since the magnetization direction is held as long as a magnetic field is not applied from the outside, a nonvolatile memory can be realized.

[0071] First, an experimental manufacturing process of the memory of the first specific example will be described.

[0072] As shown in FIG. 13, an embedded element separation region 15 made of SiO₂, an n-type diffusion region 3 and an n-type diffusion region 2 forming a drain and a source of a field effect transistor functioning as a switching element, an SiO2 gate insulating film 4, and a polysilicon gate electrode 5 are formed on a p-type silicon substrate 1.

[0073] Further, as shown in FIG. 14, an AlSiCu earth line 8 connected to the source of the field effect transistor through a tungsten plug 7 and a writing wiring 9 are provided.

[0074] Further, as shown in FIG. 15, a TMR layer 12 of a laminate structure of Co/Al₂O₃/NiFe is connected to the drain of the field effect transistor through a TiN local wiring 10 and a tungsten plug 6. Note that, in order to horizontally magnetize the TMR layer 12, the TMR layer 12 is provided above the writing line 9.

[0075] Further, as shown in FIG. 16, the other terminal of the TMR layer 12 is connected to a bit line 13 made of Ti/AlSiCu/Ti.

[0076] Further, a peripheral circuit including sense amplifiers SA1, SA2, SA3, SA4 were formed. A memory of such a structure was designed under a 0.5 μm rule (minimum possible size is 0.5 μm), and a test chip was formed which included eight units each including 4×4 memory cells.

[0077] Timing pulse signals of the respective wirings equivalent to 0 V, 3.3 V, and a clock frequency of 1 MHz as shown in FIG. 10 were inputted to one unit from the outside, and as a result of a differential operation, data of four bits (for example, “1” “0” “1” “0”) were observed. Next, when the eight units were activated every μ second (equivalent to 1 MHz) to drive the respective units, it was possible to confirm that data of four bits was outputted every μ second.

[0078] (Second specific example)

[0079] By the same experimental manufacturing process as the first specific example, a memory cell as shown in FIG. 17 was formed. The point different from the first specific example is that such a structure is adopted that a TMR layer 12 made of GdFe/A1203/GdFe laminate film is formed and a writing line 9 is provided at the side of the TMR layer 12 to cause the vertical magnetization.

[0080] As a result of an operation test similar to the first specific example, which was carried out for this memory cell, it was possible to confirm that both readout and writing were normally operated. Besides, by using the vertical magnetization film for the memory element, the element can be made minute as compared with the in-plane magnetization film, which is further preferable.