Title:

Kind
Code:

A1

Abstract:

A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (m+2) of logical stages is n=2^{m+1 } and for bit lengths n not of a binary order, the number (m+2) of logical stages is n_{bo} =2^{m+1} , where n_{bo } is the next largest binary order after n.

Inventors:

Knowles, Simon (Bath, GB)

Application Number:

10/322197

Publication Date:

08/21/2003

Filing Date:

12/17/2002

Export Citation:

Assignee:

STMicroelectronics Limited (Bristol, GB)

Primary Class:

International Classes:

View Patent Images:

Related US Applications:

Primary Examiner:

MAI, TAN V

Attorney, Agent or Firm:

SEED INTELLECTUAL PROPERTY LAW GROUP LLP (SEATTLE, WA, US)

Claims:

1. An addition circuit for adding together two binary numbers each having a length of n bits, comprising: an array of logical nodes that are arranged so that each set of logical nodes extending widthwise of the circuit form a logical stage and each set of nodes extending depthwise of the circuits forms an addition path, with each pair of adjacent addition paths forming a column; spanning paths arranged to interconnect selected logical nodes so that adjacent logical stages are connected via an interconnection level, each spanning path extending from a node in one stage across at least one column being connected to a number f of fan-out nodes in a subsequent stage, the circuit having the following configuration parameters: i) for each interconnection level the number f of fan-out nodes lies in the range 1 to 2

2. An addition circuit as claimed in claim 1 wherein for bit lengths n of a binary order the number (m+2) of logical stages is derived from the following equation:

3. An addition circuit according to claim 1 wherein for bit lengths n which are not binary orders, the number (m+2) of logical stages is derived from the following equation:

4. An addition circuit according to claim 1 wherein each logical node receives at least two signals representing bits of the same significance (i) in the binary numbers to be added, and comprises at least one logic gate.

5. An addition circuit according to claim 1 wherein each spanning path conveys one or more signals from a node of one significance in one logical stage to a node of a different significance in a subsequent logical stage.

6. An addition circuit according to claim 1 wherein the fan-out f=1 for more than one level.

7. An addition circuit according to claim 6 wherein f=1 for all levels except the mth level.

8. An addition circuit according to claim 1 wherein at least one level has maximum fan-out (f=2

9. An addition circuit according to claim 1 wherein the fan-out f=2 for at least two levels

10. A method of designing an addition circuit for adding together two binary numbers each of bit length n, the method comprising: determining the number (m+2) of logical stages in the addition circuit according to the following: for bit length n of a binary order, n=2

11. An addition circuit for an integrated circuit, comprising: a plurality of nodes, the nodes arranged in rows and columns, each row forming a logical stage, and each column forming an addition path; a plurality of spanning paths connecting nodes in one column with nodes in one or more adjacent columns and in one or more subsequent stages; and the number (m+2) of logical stages comprises: for bit lengths n of a binary order, n=2

12. The circuit of claim 11 wherein the number (m+1) of stages further comprises: for bit lengths n that are not binary orders, n

13. The circuit of claim 11 wherein spanning paths comprise metal lines arranged to interconnect selected nodes so that the adjacent logical stages are connected via an interconnection level, the circuit comprising the following configuration parameters: i) for each interconnection level the number f of fan-out nodes lies in the range of 1 to 2

14. The circuit of claim 13 wherein the number (m+1) of stages comprises: for bit lengths n that are not binary orders, n

15. The circuit of claim 14 wherein the plurality of spanning paths comprise metal lines, and wherein each node comprises at least one logic gate coupled to bits of the same significance in each operand by one or more metal wires.

16. A method for designing an addition circuit, comprising: determining the bit-length n of the operands to be added; determining the number (m+2) of logical stages in the addition circuits, comprising: for bit length n of a binary order, n=2

17. The method of claim 16 wherein determining the number of logical stages further comprises: for bit lengths n that are not binary orders, n

18. The method of claim 16 wherein determining the expected input capacitance comprises: determining the required output drive strength of the addition circuit; defining the size of the logic gates required to implement the nodes of the final stage; and determining the input capacitance of the final stage.

Description:

[0001] The present invention relates to addition circuits for adding a binary number A to a binary number B, and more particularly but not exclusively to addition circuits designed to meet particular process or application criteria.

[0002] A variety of different addition circuits are known. One basic example is illustrated in _{i }_{i }_{i }_{i }_{8 }

[0003] The bit a_{0 }_{0 }_{0}_{0 }_{0 }_{0 }_{1 }_{1 }_{1 }_{1}_{1 }_{1 }_{1}_{1 }_{1 }_{1 }_{1}_{1 }_{0}_{1 }_{1}_{1 }_{1 }_{1 }_{1}_{2 }_{2 }_{2 }_{2}_{2 }_{1}_{2 }_{2}_{2 }_{2 }_{2 }_{2 }_{1}

[0004] The output from the AND gate _{2 }_{2}_{2 }_{2 }_{2 }_{2}_{2 }_{3}_{3 }_{3 }_{3 }_{3}_{3 }_{3}_{3 }_{3 }_{3 }_{3}_{3 }_{3 }_{2 }_{3 }_{3 }_{3}_{3 }_{3 }_{2}

[0005] The output from the AND gate _{3 }_{3 }_{1}_{3 }_{3 }_{3}_{4 }_{3 }_{4 }_{4 }_{4}_{4 }_{4}

[0006] An OR gate _{4 }_{4 }_{4 }_{4}_{4 }_{3 }_{4}_{4 }_{4 }_{4 }_{4}_{5 }_{5 }_{4 }_{5 }_{5 }_{5}_{5 }_{4 }_{5 }_{5 }_{5}

[0007] An OR gate _{5 }_{5 }_{5 }_{5 }_{5 }_{4 }_{5}_{5 }_{3 }_{5 }_{5}_{5 }_{5}

[0008] The output from the OR gate _{5 }_{6}_{6 }_{6 }_{6 }_{6}_{6 }_{6}

[0009] An OR gate _{6 }_{6 }_{6 }_{6}_{6 }_{5 }_{6 }_{6}

[0010] The output from the OR gate _{6 }_{6}_{6 }_{5 }_{6}_{6 }_{6 }_{6 }_{6}_{6 }_{6 }_{3 }_{6}_{6 }_{6}

[0011] The output of the OR gate _{6 }_{7}_{7 }_{7 }_{7}_{7 }_{7}

[0012] The bit a_{7 }_{7 }_{7 }_{7 }_{6}_{7 }_{7}_{7 }_{6}_{7 }_{7}_{7 }_{7 }_{7 }_{7}

[0013] An AND gate _{7 }_{7 }_{5 }_{7}_{7 }_{7}_{7 }_{7}_{7 }_{5 }_{7}_{7 }_{7}_{7 }_{3}_{7 }_{7}_{7 }_{8}

[0014] An addition circuit that can quickly change between producing an output value A+B and output value A+B+1 or that can simultaneously provide an output value A+B and an output value A+B+1 is described in an earlier GB Patent Application No. 9813328.3.

[0015] The addition circuitry described in that application has a plurality of addition paths, with each addition path having inputs for receiving respectively bits a_{i}_{i }_{i}_{i }

[0016] By modification to the output means, the circuit can be configured to provide a number of different useful outputs, such as A+B or A+B+1; A+B and A+B+1; A−B and B−A; A−B or B−A; and modulus A−B. Thus, the circuit has a number of different useful applications.

[0017] Each addition path has a number of logical nodes in the depth direction of the circuit (input to output). Each set of nodes arranged widthwise of the circuit (that is in the direction of bit significance) forms a logical stage. Each adjacent pair of addition paths defines a column. An addition circuit of so-called “minimum depth” has the minimum number of logical stages which are required to add together the binary numbers according to their length n. Clearly, the greater the length n of binary numbers to be added, the higher is the number of stages even in a “minimum depth” circuit.

[0018] In developing a minimum depth circuit, clearly constraints are imposed on how the logical nodes can be interconnected. In GB Application No. 9813328.3, the circuit is designed so that each logical node is connected to as many logical nodes in the subsequent logical stage as possible. This connection is made via the addition path for the node and by one or more spanning path which crosses at least one column. The number of nodes in a subsequent stage to which a node of the preceding logical stage is connected by spanning paths is termed herein “fan-out”.

[0019] Thus, the circuit of the earlier application is designed with so-called maximum fan-out. This has the advantage of minimising the number of wires that are required to make the circuit, but has the disadvantage that delays between logical states are incurred as a result of the capacitance introduced by the large number of gates connected to particular wires, particularly in the later logical stages.

[0020] Another possibility is to interconnect a node of a logical stage to a unique single node of a subsequent stage, which has the advantage of reducing fan-out (to a fan-out of 1), but the disadvantage of requiring a large number of wires which increases the space requirement for the circuit.

[0021] It is desirable to be able to design an addition circuit to accommodate a number of different process and application criteria. In particular, it is desirable to facilitate the process of designing an addition circuit of minimum depth.

[0022] According to the invention there is provided an addition circuit for adding together two operands, for example, two binary numbers (A,B), each having a length of n bits. The circuit includes an array of logical nodes that are arranged so that each set of logical nodes extending widthwise of the circuit form a logical stage and each set of nodes extending depthwise of the circuits form an addition path, with each pair of adjacent addition paths forming a column. Spanning paths are arranged to interconnect selected logical nodes so that adjacent logical stages are connected via an interconnection level, each spanning path extending from a node in one stage across at least one column and being connected to a number f of fan-out nodes in a subsequent stage.

[0023] The circuit has one or more of the following configuration parameters:

[0024] i) for each interconnection level the number f of fan-out nodes lies in the range 1 to 2^{j}^{j }

[0025] ii) the fan-out f of nodes at each level is always no greater than the number f of fan-out nodes at a subsequent level,

[0026] iii) the number of columns across which a spanning path extends within an interconnection level is 2^{j}

[0027] at least one level has a fan-out number f<2^{j }

[0028] By defining a number of criteria for the addition circuit in terms of the configuration parameters referred to above, it is possible to design the addition circuit to suit the particular requirements at hand. That is, it allows designs to be constructed with fewer spanning wires and/or lower fan-out without significantly compromising speed requirements for a given circuit depth. The configuration parameters allow a number of design trade-offs to be considered each time resulting in an optimized addition circuit for the particular instant application.

[0029] The invention is particularly useful in the context of minimum depth addition circuits. For an addition circuit of minimum depth, the number (m+2) of logical stages is derived from the following equations:

[0030] n=2^{m+1 }

[0031] n_{b0}^{m+1 }_{b0 }

[0032] In the described embodiment, each logical node comprises at least one logic gate that receives at least two signals representing bits of the same significance i in the binary numbers a, b to be added.

[0033] Each spanning path can convey one or more signals from a node of one significance in one logical stage to a node of a different significance in a subsequent logical stage.

[0034] Another aspect of the invention provides a method of designing an addition circuit for adding together two binary numbers (A,B) each of bit length n. The method includes:

[0035] determining the number (m+2) of logical stages in the addition circuit according to the following:

[0036] for bit length n of a binary order, n=2^{m+1 }_{b0}^{m+1 }_{b0 }

[0037] for each of said logical stages allocating a set of virtual nodes, the virtual nodes forming potential addition paths depthwise of the circuit and adjacent addition paths forming a column;

[0038] determining for each logical stage its expected input capacitance; and

[0039] defining spanning paths wherein the spanning paths constitute an interconnection level between adjacent logical stages, wherein definition of the spanning paths is carried out in accordance with the following configuration parameters and depending on the expected input capacitance of each stage:

[0040] i) for each interconnection level the number f of fan-out nodes in a subsequent stage to which a node of a preceding stage is connected lies in the range 1 to 2^{j}^{j }

[0041] ii) the fan-out f of nodes at each level is always no greater than the fan-out f of nodes at a subsequent level,

[0042] iii) the number of columns across which a spanning path extends within an interconnection level is 2^{j}

[0043] at least one level has a fan-out number f<2^{j }

[0044] A number of different specific examples are possible. By way of illustration, the following particular examples are mentioned, but this is in no way a comprehensive list of all of the possible options.

[0045] An addition circuit wherein the fan-out f=1 for more than one level.

[0046] An addition circuit wherein f=1 for all levels except the mth level.

[0047] An addition circuit wherein at least one level has maximum fan-out f=2^{j }

[0048] An addition circuit where the fan-out f=2 for at least two levels.

[0049] For a better understanding of the present invention and to understand how the same may be brought into effect, reference will now be made by way of example only to the accompanying figures.

[0050]

[0051]

[0052]

[0053]

[0054]

[0055] Referring to

[0056] Ni,k where i is the bit significance of the node and k is an index defining the depth of the node within the addition circuit in a manner, which will become clearer in the following.

[0057] The nodes N are arranged so that each set of logical nodes extending widthwise of the circuit forms a logical stage. That is, the nodes N

[0058] Depthwise of the circuit, each set of nodes forms an addition path. Each pair of adjacent addition paths constitutes a column labelled C

[0059] The spanning paths in level

[0060] The composition of each node in terms of its logical gates and the function of those logical gates can be seen by comparing _{2 }_{2}_{5}_{5 }_{5}_{0 }_{7}_{0 }_{7}

[0061]

[0062] As already mentioned, a problem that exists with this circuit is the high fan-out for the last and the next-to-the last level, which imposes signal delays through the interconnection levels. One way of avoiding this would be to construct a circuit along the lines illustrates in the node diagram of

[0063] The inventor has determined that there are a number of other design options for a bit length of n=8 and a minimum depth addition circuit, which are illustrated in

[0064] i) For each interconnection level Lj, the number f of fan-out nodes lies in the range 1 to 2^{j}^{j }

[0065] ii) The number f of fan-out nodes at each level is always no greater than the number f of fan-out nodes at a subsequent level.

[0066] Thus, in

[0067] iii) The number of columns across which a spanning path extends within an interconnection level is 2^{j}

[0068] The addition circuits of

[0069]

[0070] The principles of the invention can be readily extended to addition circuits for adding binary numbers of different lengths. The invention also applies to so-called minimum-depth addition circuits, where the number of stages in the addition circuit is determined according to the following criteria:

[0071] for bit lengths n of a binary order, the number m+2 of logical stages is derived from the following equation:

^{m+1}

[0072] for bit lengths n which are not binary orders, the number m+2 of logical stages is derived from the following equation: n_{bo}^{m+1 }_{bo }

[0073] As will be apparent, in the preceding example m=2, the number of interconnection levels (index j) is m+1=3 and the number of logical stages (index k) is m+2=4.

[0074] In designing an addition circuit using the node array diagrams illustrated in

[0075] A method of designing an addition circuit will now be described. The binary length n of the numbers to be added is first specified. Then, the number of logical stages in the addition circuit is determined according to the above-defined criteria for a minimum-depth addition circuit. The required output drive strength of the addition circuit is established, and this defines the size of the logic gates requires to implement the nodes of the final stage. The size of the logic gates used to implement the nodes of the final stage determines the input capacitance of that stage. At this point, the design options available according to the configuration parameters of the present invention can be considered to provide a number of different options for the addition circuit. For each option or a selected group of these options, the capacitance of the spanning paths in the interconnection level to the final stage can be calculated. The choice of a spanning configuration in terms of the number of wires versus the extent of fan-out determines the size of logic gates at the driving level, which in turn determines the input capacitance as seen by the preceding level. Thus, a recursive design method is implemented to determine an optimum addition circuit for the application in hand.

[0076] The invention thus provides a number of different design options for addition circuits that allow a designer more freedom than has hitherto been the case in designing addition circuits.

[0077] Although representative embodiments of the invention have been illustrated and described, it will appreciated that various changes can be made therein without departing from the spirit and scope of the invention. Thus, the invention is to be limited by the scope of the claims that follow.