IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb—Sn solder balls are employed for joining.
These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy.
Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.
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[0001] This patent application is related to U.S. patent application Ser. No. 08/476,475, entitled, “METHOD FOR FORMING REFLOWED SOLDER BALL WITH LOW MELTING POINT METAL CAP”, filed on Jun. 7, 1995, U.S. patent application Ser. No. 08/476,474, entitled, “REFLOWED SOLDER BALL WITH LOW MELTING POINT METAL CAP”, filed on Jun. 7, 1995, U.S. patent application Ser. No. 08/476,466, entitled, “METHOD FOR MAKING DIRECT CHIP ATTACH CIRCUIT CARD”, filed on Jun. 7, 1995, and U.S. patent application Ser. No. 08/476,472, entitled, “DIRECT CHIP ATTACH CIRCUIT CARD”, filed on Jun. 7, 1995, presently assigned to the assignee of the instant application and the disclosure of which is incorporated herein by reference.
[0002] The present invention relates generally to an improved and cost saving Direct Chip Attach (DCA) on Flexible circuit carriers using Flip Chip Attach (FCA) technology. More particularly, the invention encompasses a structure where at least one Integrated Circuit Chip can be directly attached to a flexible substrate. This direct attachment can be done using C4 (Controlled Collapsed Chip Connection) technology by capping the already reflowed solder balls and forming a eutectic solder composition. A method for such direct chip attachment to the flexible card is also disclosed.
[0003] Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding challenge to improve chip and chip connections in order to remain competitive. Whereas significant process improvements are being made by reducing process variability, process improvements alone are not sufficient to increase both yield and reliability of these products. Further, the packaging technology has not been able to keep pace with IC (Integrated Circuit) chip miniaturization for performance improvements.
[0004] Electronic products typically comprise of plurality of components. The packaging of these components follow a hierarchy where an Integrated Circuit (IC) chip comprising of semiconductor micro-devices are connected (1st level assembly) to carriers made of ceramic or organic laminates comprising one or several layers of metal interconnection lines. These carriers may also contain some other discrete devices like capacitors, resistors etc. Thus assembled carriers with IC chips, along with some kind of sealing and cooling methodology, are called modules.
[0005] These modules, in turn, are connected to cards (2nd level assembly) usually made of organic laminates with printed circuits on either side of the card.
[0006] These cards are then connected to boards (3rd level assembly). Such 3 levels of hierarchy is required in many electronic applications, such as, in computer CPUs where performance of complex functions is required.
[0007] Increased integration in present day IC chips require product miniaturization by eliminating first, second or both levels of packaging. For example, in Direct Access Storage Discs (DASD), read/write functions provided by a static region, comprised of IC chips on an input card, are cross linked to a dynamic region, comprised of memory discs, via Flexible Printed Circuit Boards. A close proximity of static and dynamic regions is required to increase the performance of such DASD. This requires direct bonding of IC chips on Flexible circuit carrier connected to the disc drive.
[0008] The Tape Automated Bonding (TAB) is the most common method presently used for chip attachment on Flexible circuit carrier because it is also the most common method for first level packaging and it is suitable for mounting on flexible base.
[0009] However, TAB is not capable of taking full advantage of the Very Large Scale Integration which not only requires close spacing of I/O pads but also requires an array pattern to accommodate the vast number of I/O pads.
[0010] The TAB itself is a first level of packaging, hence TAB mounting of chips on Flexible circuit carrier precludes it from the Direct Chip Attach technology.
[0011] Another shortcoming of TAB is that it requires additional space to accommodate the wire leads, this limits its capability in bringing the static and dynamic regions close enough.
[0012] Yet another limiting factor for use of TAB is difficulty in testing and/or burning-in of these mounted chips; this limits the yield thus making the product expensive.
[0013] Still yet another shortcoming is that rework is economically unfeasible.
[0014] These limitations necessitate use of a C
[0015] The C4 or Controlled Collapse Chip Connection technology has been successfully employed for 1st level assembly of chip on ceramic carriers. The C4 technology is described in detail by many authors, see for example, Microelectronics Packaging handbook, edited by, Rao R. Tummala and Eugene J. Rymaszewski, pages 366-391 (1989), the disclosure of which is incorporated herein by reference.
[0016] The C4 interconnection is comprised of two main elements, a solder wettable pad called Ball Limiting Metallurgy (BLM), and a ball of solder. The BLM is comprised of an adhesive layer like Cr or TiW, and a solder reflowable layer like copper or nickel. The BLM materials and their thicknesses are judiciously chosen to provide good and reliable electrical, mechanical and thermal stability to interconnect structure. The solder material used for C4 is preferably a low percentage (about 2 percent to about 10 percent) tin alloyed with lead. This combination is used:
[0017] (i) to prevent melting of the reflowed solder ball or C4 during the next level of packaging interconnection,
[0018] (ii) to reduce reaction between copper of BLM and tin, as high stresses resulting from excessive copper-tin intermetallic imparts a high stress concentration on underlaying passivation, and,
[0019] (iii) for better thermal fatigue characteristic offered by lower Sn (tin) percentage.
[0020] Presently, there are two problems that limit the use of current C4 technology for 2nd or higher level assembly, or, for Direct Chip Attach on card. First it limits the interconnection to Pin-Through-Hole (PTH) technology and precludes the use of space saving Surface Mount Technology (SMT), because a joining temperature higher than melting point of the SMT solder is required. Second, the relatively high joining temperature (between about 340° C. to about 380° C.) precludes the use of organic card material.
[0021] There are two ways to lower the joining temperature for DCA. One approach is to provide an eutectic (or lower melting) solder on a card metallization. A method pertaining to this approach is described in U.S. Pat. No. 4,967,950 to Legg and Schrottke, which is presently assigned to the assignee of the instant patent application. Legg and Schrottke describes a general scheme for attaching IC chips to flexible substrate (laminate) using C4s. The substrate is “tinned” with an alloy of eutectic composition in its contact region with the solder balls on the base of the chip.
[0022] The method of pre-coating the card, or an organic carrier, by eutectic solder is taught by Fallon et al., U.S. patent application Ser. No. 08/387,686, entitled “Process for Selective Application of Solder to Circuit Packages”, filed on Feb. 13, 1995, and the disclosure of which is incorporated herein by reference. In this method, eutectic solder is electroplated on copper conductors of printed circuit card precisely where the Chip C4 bumps would make contact.
[0023] Another method of pre-coating the card, or an organic carrier, by eutectic solder is taught by Nishimura, U.S. Pat. No. 5,238,176, entitled “Method and apparatus for forming bump”, assigned to the assignee of the instant patent application, and the disclosure of which is incorporated herein by reference. In this method, precise amount of eutectic solder, in liquid state, is injected at sites on copper conductors of laminated circuit card through an injector head having openings pertaining to the card part number used. The above methods are limited to rigid substrates.
[0024] A method for flexible substrates, which matches the Legg and Schrottke's scheme of “tinning” the substrate with eutectic alloy, is shown by Milkovich et al., in U.S. patent application Ser. No. 08/071,630, entitled “Manufacturing Flexible Circuit Board Assemblies with Common Heat Spreaders”, filed on Jun. 3, 1993, and assigned to the assignee of the instant patent application, and the disclosure of which is incorporated herein by reference. In this method, “decals” of eutectic solder balls with required footprint are first formed which is subsequently transferred on the flexible circuit carrier. Decals are formed by electroplating solder balls on a stainless steel plate. This method requires a photo-imageable solder mask on the Flexible circuit carrier circuit, holes corresponding to the required footprint are developed out in this mask. The decals are transferred by placing the flipped stainless steel plate on flexible circuit carrier card and reflowing. Flexible printed circuit cards are typically made of polyimides, for example Pyralux (Trade Mark of E. I. duPont de Nemours & Co., Inc.). Using this technique, Milkovich et al., “Double Sided Flexible Carrier with Discretes and Thermally Enhanced FCA/COF” IEEE 43rd ECTC Proceedings, June 1993, pages 16-21, have demonstrated methods of circuitization and device attachments on both sides of the flexible circuit carrier; the disclosure of which is incorporated herein by reference. One of the disadvantage of this method is poor yield.
[0025] A second approach for lowering the joining temperature for Direct Chip Attach (DCA), is to provide a low melting Solder On Chip (SOC) C4 rather than on the carrier conductor. Carey et al., in U.S. Pat. No. 5,075,965 and Agarwala et al., in U.S. Pat. Nos. 5,251,806 and 5,130,779, which are presently assigned to the assignee of the instant patent application, and Japanese Patent Publication No. 62-117346 to Eiji et al., describe various schemes to provide low melting solder on chips. Carey et al., in U.S. Pat. No. 5,075,965, disclose a method, where an inhomogeneous, anisotropic column consists of lead rich bottom and tin rich top of sufficient thickness to form eutectic alloy. The resulting as-deposited and un-reflowed column is then joined onto the card's conductor.
[0026] To circumvent the thermodynamically driven tendency for interdiffusion, Agarwala et al., in U.S. Pat. Nos. 5,251,806 and 5,130,779, showed a structure where the low melt component is separated from the high melt component by interposing a barrier metal layer. This structure does show a hierarchy of solder material, however, in this structure the column of high melting solder never get reflowed. Because, the stacked solder does not get reflowed there is no metallurgical reaction between the solder stack and the adhesive pad of BLM which is known to cause poor mechanical integrity of the C4 joint.
[0027] Eiji et al., in Japanese Patent Publication No. 62-117346, describes an anisotropic column structure of low and high melting solders. The basic objective of this invention is essentially to provide an increase height of a solder joint rather than to provide a low melting solder joining process. In Eiji et al., a high-melting point metallic layer is secured to a chip and a substrate and a low-melting point metallic layer is then formed. the two low-melting point metallic layers are then joined and thereby the chip is joined to the substrate.
[0028] IBM Technical Disclosure Bulletin, entitled “Indium-Lead-Indium Chip Joining”, W. A. Dawson et al., vol. 11, No. 11, page 1528 (April 1969), discloses the standard capping of lead with either indium or tin for diffusion bonding. In order to alleviate the problem of chip collapse onto the surface of the substrate an intermediate temperature is employed.
[0029] For the purpose of this invention a bump completely composed of low melting composition is a feature to be avoided as the high tin content reacts with all of the copper of the adhesive layer (BLM) giving a thick intermetallic layer. High stresses of reacted BLM have been known to cause solder pads to fall off and to create insulation cracking. The eutectic solder bumps also have poor electromigration and thermal fatigue lifetime. It is also known that low melting eutectic solder suffers from void formation due to thermal migration which causes circuit failure.
[0030] Yet another drawback of inhomogeneous, anisotropic solder column is that this structure is unfavorable for electrical tests of circuitry before joining the chips on carriers as the electrical probes gouge into the low melt cap during testing and destroy the cap. Furthermore, for the chip burn-in it is also not feasible to use any of the known multilayered solder balls, as the temperature that is generally used is between about 120° C. and about 150° C. for burn-in which will cause inter diffusion of the low and the high melt components even before the joining operation begins.
[0031] This invention relates generally to interconnection in electronic circuit packages, and more particularly shows a new solder interconnection technology to make a Direct Chip Attachment (DCA) on Flexible organic circuit carrier.
[0032] According to the present invention a method is provided for preparing the flexible circuit carrier card for direct device attachment using low melting Solder On Chip (SOC) where the low melting eutectic alloy is formed during joining operation and is localized at the tip of the standard high melting C4 ball.
[0033] The invention is a novel method and structure for providing direct device attach to flexible circuit card using a novel solder interconnection scheme.
[0034] Accordingly, it is a purpose of the present invention to provide a method for preparing the flexible circuit carrier card for direct device attachment using a novel solder interconnection scheme.
[0035] Another purpose of this invention is to provide a method for simultaneously joining devices on Flexible card using the DCA/SOC, the method of the instant, along with various Flip Chip, SMT and/or BGA (Ball Grid Array) technologies.
[0036] It is a further purpose of the present invention to provide a method of directly attaching one or more of devices using one or more of joining technologies and having flexibility to discretely remove and replace devices joined with various technologies.
[0037] Another purpose of this invention is to provide a Flexible circuit card/device assembly which has increased performance.
[0038] Yet another purpose of this invention is to provide for a Flexible circuit carrier card which is low in cost, easy to build and possesses high reliability.
[0039] Still yet another purpose of this invention is to provide a Flexible circuit carrier card with mounted devices which has low profile, is compact in design and has low weight.
[0040] Yet another purpose of this invention is to have a Flexible card which is compatible with wafer level electrical test and burn-in.
[0041] Therefore, in one aspect this invention comprises a method of directly attaching an electronic device onto a flexible circuit carrier, said method comprising the steps of:
[0042] (a) providing said electronic device with at least one reflowed solder ball, wherein said reflowed solder ball has at least one coating of at least one low melting point metal to form a metallic cap,
[0043] (b) adhering at least one layer of at least one stiffener sheet with at least one thermo-plastic adhesive onto at least one surface of a flexible sheet,
[0044] (c) forming at least one electrically conductive metal line on said at least one surface of said flexible sheet,
[0045] (d) coating at least a portion of said flexible carrier with at least one insulator material, and removing selective portions of said insulator material and exposing selective portions of said metal line, and forming a flexible circuit carrier,
[0046] (e) screening eutectic solder paste to coat selective sites on said flexible circuit carrier,
[0047] (f) placing said flexible circuit carrier on an assembly fixture to hold said flexible circuit carrier,
[0048] (g) dispensing at least one solder flux at selective sites on said flexible circuit carrier,
[0049] (h) aligning and placing said electronic device onto said flexible circuit carrier, such that reflowed solder ball with metallic cap makes contacts with said solder flux, and upon heating forms an electrical connection between said electronic device and said flexible circuit carrier.
[0050] In another aspect this invention comprises a flexible electronic carrier comprising a flexible device carrier and at least one electronic device electrically connected thereto by at least one solder ball, wherein said solder ball has a cap of at least one low melting point cap forming a eutectic.
[0051] The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The drawings are for illustration purposes only and are not drawn to scale. Furthermore, like numbers represent like features in the drawings. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
[0052]
[0053]
[0054]
[0055]
[0056]
[0057]
[0058]
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[0060]
[0061] The invention basically encompasses a flexible circuit carrier with metallic conductor lines, such as, copper. Openings are made at sites which will be electrically connected to an electronic device using reflowed solder with a metallic cap. Ashing of the surface of the flexible circuit carrier could also be done to improve the adhesion and the flow of encapsulants. Solder paste could be screened for SMT, solder balls could be placed for BGA, or, solder could also be placed by solder injection for various flip chip attach methods. Likewise, either one or both surfaces of the flexible circuit carrier could be prepared to secure various electronic devices.
[0062] The invention also encompasses the formation of a direct chip attach (DCA) on the flexible circuit carrier surface. This is done by aligning the solder interconnections with a cap of low melting point metal on the chip with the corresponding footprints on the flexible circuit carrier. The assembly is then held at a bias temperature of about 150° C. and then individual chips are heated, preferably with Infra Red (IR) heat source to a temperature of between about 190° C. to about 220° C. in a nitrogen or a forming gas environment. The assembly is then cooled and the chip is preferably encapsulated with an epoxy based encapsulant, such as, HYSOL 4511, Trade Name used by Dexter Hysol of California, USA.
[0063] An advantage of this invention is the fact that the method is applicable for all levels of packaging, i.e., for highest level packaging, involving chip joining to motherboard or flexible circuit carrier cards or PCMCIA (Personal Computer Memory Card International Association) cards.
[0064] This invention basically came about as an unexpected result which showed that low melting point solder that is deposited atop a reflowed solder mass alloys only with enough solder mass to form a volume of eutectic alloy. It was also found that relatively little or no further interdiffusion took place even after multiple times of eutectic melting cycles. This is believed to be due to that fact that the amount of low melting point atop the solder mass was equivalent to eutectic composition for the deposited mass of low melting point metal. Thus, a desired volume of eutectic liquid atop a solid solder mass is formed without any need for a barrier. A volume of eutectic liquid remains present, whenever the joint temperature is raised to eutectic temperature, even after joining on copper interconnections of circuit carrier; this liquid formation at the joint interface presents an ideal condition for easy removal of the joined chip for the purposes of chip replacement without mechanically or thermally affecting other components on the board.
[0065] As stated earlier that the solder interconnections using solder balls having a cap of low melting point metal allows for making a low temperature chip attachment directly to any of the higher levels of packaging substrates. After the solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of metal, such as tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, on top of the solder ball even after multiple low temperature reflow cycles.
[0066] This method does not need tinning of the carrier or substrate to which the chip is to be joined, which makes this method economical.
[0067] It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires. This liquid fillet formation results in substantial thermal fatigue life improvement for reduced stress at interface; and secondly, provides an easy means to remove chip for the purpose of chip replacement and field repairs.
[0068] These methods, techniques and metallurgical structures enables direct attachment of devices of any complexity to any substrate and to any level of packaging hierarchy; thereby, making the products more economical and more compact as well as resulting a better performance.
[0069] Referring now to the drawings, wherein like reference numerals represent the same or similar parts throughout,
[0070] After the circuit carrier substrate
[0071] As shown in
[0072] The organic material
[0073]
[0074] The surface of the organic material
[0075]
[0076]
[0077] An IC chip
[0078] This assembly is then reflowed, preferably, in a belt type furnace. However, heat for the solder reflow could be provided by at least one focused IR lamp. It is preferred that the belt speed and zone temperatures are adjusted so as to give a temperature profile where the assembly of
[0079]
[0080]
[0081]
[0082] The solder ball
[0083] It should be apparent that the IC chip
[0084] It is preferred that the high melting point solder ball is between about 2 percent to about 10 percent Sn, with the balance being Pb, on the chip with at least one capping layer of low melting point metal, such as, tin, thereby, providing eutectic solder at the tip of the high melting solder ball.
[0085] To those skilled in the art, it should be obvious that the flexible circuit carrier substrate
[0086] The electronic devices typically have electrically conductive feature, such as pad, pins, etc., and wherein material for the electrically conductive features is selected from a group comprising Au, Co, Cr, Cu, Fe, Ni, TiW, phased Cr and Cu, and alloys thereof.
[0087] It is preferred that at least one layer of at least one low melting point metal is formed on the solder ball by a method selected from a group comprising Radio Frequency evaporation, E-beam evaporation, electroplating, electroless plating or injection.
[0088] And, wherein the at least one low melting point metal s selected from a group comprising of bismuth, indium, tin or alloys thereof.
[0089] It is preferred that at least one low melting point metal, caps between about 10 percent to about 90 percent of the exposed surface of the solder ball, and preferably caps between about 20 percent to about 80 percent of the exposed surface of the solder ball, and more preferably caps between about 30 percent to about 50 percent of the exposed surface of the solder ball. However, in some cased the low melting point metal could completely envelope the solder ball.
[0090] The average thickness of the at least one low melting point metal cap is between about 15 to about 50 micrometers.
[0091] It should be appreciated that other materials for the flexible circuit carrier could be used, such as, the material for the flexible circuit carrier could be selected from a group comprising polyimides, poly tetra flouro ethylene (PTFE), polyester or resin-impregnated fabrics, to name a few.
[0092] While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.