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DE102019006294B3 Multi-Die-Chip  
Multi-Die-Chipwobei nur ein Lithographie-Maskensatz für die Chipherstellung benutzt wird und unterschiedlich große Multi-Die-Chips mit 1..n Einzel-Dies aus einem Wafer herausgetrennt werden...
DE102016200965B4 Halbleiterstruktur mit mindestens einer elektrisch leitfähigen Säule, Halbleiterstruktur mit einem Kontakt, der eine äußere Schicht einer elektrisch leitfähigen Struktur kontaktiert und Verfahren für ihre Herstellung  
Eine Halbleiterstruktur (100), die umfasst:ein Substrat (101);einen ersten Transistor (123) und einen zweiten Transistor (407), wobei der erste Transistor (123) eines von einem p-Kanal-Transistor...
DE102013108946B4 Halbleitervorrichtung  
Halbleitervorrichtung, umfassend:einen Halbleiterkörper (505) mit einer ersten Seite (512) und einer zur ersten Seite (512) entgegengesetzten zweiten Seite (517),einen ersten Kontakttrench (510),...
DE102019112030A1 Method for structuring a substrate  
A method for structuring a substrate is specified, in particular structuring by means of selective etching in the semiconductor and IC substrate industry, in which the following steps are carried...
DE102015106598B4 Capacitor with fuse protection  
Integrated circuit chip (20) with: active circuits having a first power node (26, 102) and a second power node (28, 106); a first capacitor (86, 88, 90) formed in a first dielectric layer (92) of...
DE102020101284A1 PROCEDURE AND STRUCTURE FOR SEMICONDUCTOR INTERCONNECT  
One method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature. The method further includes forming a...
DE102013107635B4 Damascene structure with first and second etch stop layers and method for forming a connection structure  
Damascus structure, which has: a lower conductive element (120) in a lower low-k dielectric layer (110); a first etch stop layer (ESL) (130, 140) over the lower conductive element (120), the first...
DE102020106732A1 METAL OXYCARBIDE RESISTS AS PLUGS TO BE LEAVED  
Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive...
DE102019205376A1 Establishing an ohmic contact and an electronic component with an ohmic contact  
The invention relates to a method for producing an ohmic contact for an electronic component, a layer (3) consisting of a semiconductor being applied directly or indirectly to a substrate (1),...
DE102016114705B4 Etch stop layer for semiconductor components  
Semiconductor device with: a substrate (102); a first conductive feature (106A, 106B) over a portion of the substrate (102); an etch stop layer (110) over the substrate and the first conductive...
DE112014006136B4 Semiconductor component  
Semiconductor component comprising: a heterojunction bipolar transistor (BT); wherein the bipolar transistor comprises: a collector layer (3), a base layer (4) formed on the collector layer (3),...
DE102017113930B4 Method for producing a substrate via in a semiconductor substrate  
A method comprising: Forming a first conductive layer (38) in a lower section of a dummy via (33) in a semiconductor substrate (30) using first deposition parameters such that the first conductive...
DE102020107035A1 IC comprising back-end-of-line (BEOL) transistors with crystalline channel material  
IC component comprising back-end-of-line (BEOL) transistors with crystalline channel material. A crystalline BEOL seed can be formed over a dielectric layer that has been planarized over a...
DE102020106724A1 ELECTRONIC COMPONENT PACKAGE WITH A CAPACITOR  
A substrate for an electronic component can comprise a first layer, a second layer, and can comprise a third layer. The first layer can comprise a capacitive material, and the capacitive material...
DE102019129996A1 PROCEDURE OF MAKING AND PACKING A SEMICONDUCTOR THIS  
A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer (1000) having a sealing ring region (120, 130), forms a first interlayer insulating film (20)...
DE102018206436B4 Wiring trenches coated with cobalt and barrier liners over cobalt-filled via structures and corresponding manufacturing processes  
Structure (10 ", 10 '") comprising: a via structure (22a) filled with cobalt (26); and a wiring trench (22b) over the via structure (22a), wherein the wiring trench (22b) is thinly coated with...
DE102018200438B4 Fully aligned via structures  
Structure (10, 10 ') comprising: a plurality of conductive structures (14a, 14b) formed in a dielectric material (12) with minimal structure size, each comprising a recessed conductive material...
DE102016113020B4 Semiconductor components and methods of forming a semiconductor component  
A semiconductor device comprising: a crack propagation prevention structure located at an edge region of a wiring layer stack located on a semiconductor substrate of the semiconductor device, the...
DE102015107422B4 Integrated circuit with a slot via and method for its manufacture  
An integrated circuit comprising: a first conductive line (112) on a first metal level of the integrated circuit; a second conductive line (116) on a second metal level of the integrated circuit,...
DE102014102087B4 CONTACT SPOT OVER PROCESS CONTROL / MONITORING STRUCTURES IN A SEMICONDUCTOR CHIP  
Semiconductor chip, comprising: a semiconductor substrate having an edge region (106) surrounding an active region (104), the active region (104) containing devices of an integrated circuit; Trace...
DE102012111786B4 Hybrid connection establishment and method of making the same  
Component that has: a first low-k dielectric layer (24); a copper-containing via (32) in the first low-k dielectric layer (24); a second low-k dielectric layer (46) over the first low-k dielectric...
DE102020104981A1 SELF-ALIGNED GATE END CAP (SAGE) ARCHITECTURE WITH LOCAL INTERMEDIATE CONNECTIONS  
Self-aligned gate end cap (SAGE) architectures with local interconnects and methods for fabricating SAGE architectures with local interconnects are described. In one example, an integrated circuit...
DE102020103386A1 SELF-ALIGNED GATE END CAP (SAGE) ARCHITECTURE WITH GATE OR CONTACT PLUG  
Self-aligned gate end cap (SAGE) architectures with gate or contact plugs and methods for fabricating SAGE architectures with gate or contact plugs are described. In one example, an integrated...
DE102016118811B4 Integrated circuits with staggered conductive features and methods of configuring an integrated circuit layout  
An integrated circuit comprising: at least one first conductive feature (130; 220; 530) having at least one end (144; 234; 534); at least one second conductive feature (140; 230; 540) having at...
DE102016100323B4 Reduce dual damascene warpage in integrated circuit structures  
Integrated circuit structure with: a first low-k dielectric layer (42) having a first k value; a second low-k dielectric layer (48) having a second k-value that is less than the first k-value and...
DE102014116262B4 Semiconductor devices and methods of making them  
A semiconductor device comprising: a first contact point (5) which is arranged on an upper side of a workpiece, a second contact point (15) which is arranged on the top of the workpiece, an...
DE102014113917B4 Contact pad structure, electronic component and method for producing a contact pad structure  
A contact pad structure (200) comprising: a dielectric layer structure (202); at least one contact pad (204) which is in physical contact with the dielectric layer structure (202); wherein the at...
DE102014111783B4 Stacked integrated circuits with redistribution lines and methods of making them  
An integrated circuit structure comprising: a first semiconductor chip (110 ') comprising: a first substrate (102); a plurality of first dielectric layers (104) underlying the first substrate; a...
DE102014101074B4 Vias and methods of their formation  
Semiconductor chip, which has: a substrate (10); a component area which is arranged in or above the substrate (10); a first doped region (30, 40) disposed in the device region; a contact layer...
DE102012219376B4 Semiconductor device with local transistor interconnection lines  
A semiconductor device (20) comprising: a semiconductor substrate (22); a first transistor (24a) and a second transistor (24b) which are formed on the semiconductor substrate (22), the transistors...
DE102020102814A1 Self-aligned local interconnections  
In some embodiments, a semiconductor device structure is formed using an angled etch to remove material to expose a portion of an adjacent conductor. The space formed when the material is removed...
DE102017120565B4 THROUGH CONTACTS FOR INTERMEDIATE CONNECTIONS BASED ON COBALT AND PROCESS FOR THEIR PRODUCTION  
Interconnect structure (100A, 100B, 100C) with: a conductive structural element (60, 62, 64) comprising cobalt; and a via (70, 72, 74) which is arranged on the conductive structure element (60,...
DE102015114620B4 Wafer-Level Package (WLP) and its training method  
A semiconductor device structure (100) comprising a substrate (102); a conductive pad (132) formed on the substrate (102); a protective layer (130, 140) formed over the conductive pad (132); a PPI...
DE102013103011B4 A chip arrangement and a method for forming a chip arrangement  
Having a chip arrangement: • a first chip carrier (104), having a first chip carrier upper side (106) and a first chip carrier lower side (108); • a second chip carrier (112), having a second chip...
DE102013103976B4 Semiconductor device with self-aligned connections and blocking sections  
Component comprising: a first interlayer dielectric layer (312) disposed over a substrate (310), the first interlayer dielectric layer (312) having a first conductive layer (316) having first and...
DE102011088581B4 Process for producing housing connections and component produced therewith  
Procedure with: Providing a carrier substrate (120) having a first (122) and a second main surface (124); and Forming a connection (170) through the first (122) and the second main surface (124)...
DE102020101535A1 High voltage device  
We disclose herein a high voltage device comprising: a first electrode; a second electrode disposed below and spaced from the first electrode; and a dielectric layer between the first and second...
DE102019219072A1 DUMMY FILLING SCHEME FOR USE WITH PASSIVE DEVICES  
Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure comprises a semiconductor substrate, a...
DE102019218942A1 Connection structures with air gaps and connections covered with a dielectric  
Structures comprising connections and methods of forming a structure comprising connections. A metallization level comprises a metallization level with a first connection with a first upper...
DE102015012766B4 Electrical contact structure with diffusion barrier for an electronic device and method for producing the electrical contact structure  
Electrical contact structure (1) for an electronic device, the electrical contact structure comprising: - a first structural layer (2); - a second structural layer (6) which extends over the first...
DE102013109523B4 Product with a variable resistance layer and process for its manufacture  
Product comprising: a first electrode (112) having an upper surface (112a); a second electrode (114) having a side wall (114b) and a bottom surface (114a) over the top surface (112a) of the first...
DE102019132101A1 CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE GATE TAPS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE MANUFACTURING  
Contact-over-active-gate (COAG) structures with conductive gate taps are described. In one example, an integrated circuit structure includes a plurality of gate structures over a substrate, each...
DE102014115934B4 Two-step formation of metallizations  
Integrated circuit structure that includes: - a first conductor track (32); - a dielectric layer (42) over the first interconnect (32); - a diffusion barrier layer (50) in the dielectric layer...
DE102019130925A1 MASKLESS AIR GAP ENABLED BY A SINGLE DAMASCENE PROCESS  
A method of manufacturing an integrated circuit includes forming one or more conductive features supported by pillars of a first insulation layer in a first metal layer. One or more vias are...
DE102019122665A1 Semiconductor device  
A semiconductor device includes a first semiconductor structure (S1) that includes circuit devices (120) and first bond pads (180); and a second semiconductor structure (S2) connected to the first...
DE102012219769B4 Method for making an electrical via in a substrate  
Method for producing an electrical via (WDK) in a substrate (2) with a front side (V) and a back side (R) with the steps: Forming an etch stop layer (IU, 15 ') on the front (V) of the substrate...
DE102015114904B4 Semiconductor device structures and method for forming a semiconductor device structure  
A semiconductor device structure comprising: a metal gate stack (123) over a semiconductor substrate (100), the metal gate stack (123) comprising a gate dielectric layer (118), a work function...
DE102015112914B4 Structure of a fin field effect transistor device (FinFET device) with interconnection structure  
Semiconductor device structure comprising: a first metal layer (104) formed over a substrate (102); a dielectric layer (112) formed over the first metal layer (104); an adhesive layer (130) formed...
DE102013109881B4 Method for producing a chip arrangement and method for producing a chip assembly  
Method (100) for producing a chip arrangement, the method comprising: Forming (110) a hole in a carrier (504) with at least one chip (506), wherein forming a hole in the carrier (504) comprises:...
DE102013103206B4 Via structure and method  
Device comprising: a dielectric interlayer (115) formed on a first side (101) of a substrate (102); a first metallization layer formed over the intermediate dielectric layer (115), the first...