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9372946 Defect injection for transistor-level fault simulation  
Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection....
9038010 DRC format for stacked CMOS design  
The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer...
9038004 Automated integrated circuit design documentation  
A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at...
9032350 Semiconductor device  
A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon...
9032348 Physics-based reliability model for large-scale CMOS circuit design  
This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation...
9032349 Crosstalk analysis method  
One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program;...
9026960 Systems and methods for lithography-aware floorplanning  
The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method...
9026981 Dielectric reliability assessment for advanced semiconductors  
Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data...
9026970 Prioritized design for manufacturing virtualization with design rule checking filtering  
An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked...
9026971 Multi-patterning conflict free integrated circuit design  
The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on...
9015644 Crosstalk analysis method  
An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program;...
9009639 Method and system for enhanced integrated circuit layout  
An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a mirror of the first...
9009632 High performance design rule checking technique  
Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a...
9003341 Method for determining interface timing of integrated circuit automatically and related machine readable medium thereof  
A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface...
9003344 Generating pattern-based estimated RC data with analysis of route information  
A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed....
8997032 Method for input/output design of chip  
Method for input/output (IO) design of a chip, including: according to a signal IO pin sequence and associated driving parameters, sequentially placing a signal IO cell in the IO design associated...
8996348 System and method for fault sensitivity analysis of digitally-calibrated-circuit designs  
An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the...
8990760 Cell-aware fault model generation for delay faults  
Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one...
8984458 Dynamic rule checking in electronic design automation  
Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of...
8984459 Methods and apparatus for layout verification  
Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a...
8983632 Function block execution framework  
A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected...
8978002 Rapid expression coverage  
This application discloses simulating a circuit design with a test bench and determining an expression coverage in the circuit design by the test bench with a rapid expression coverage process....
8972917 System and method for generating a field effect transistor corner model  
Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial...
8966418 Priority based layout versus schematic (LVS)  
An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical...
8966427 Systems and methods for integrated circuit C4 ball placement  
Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to...
8959468 Fault injection of finFET devices  
Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and...
8954911 Circuit analysis device and circuit analysis method  
A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory...
8954910 Device mismatch contribution computation with nonlinear effects  
A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated...
8943458 Determining chip burn-in workload using emulated application condition  
Various embodiments include approaches for determining burn-in workload conditions for an integrated circuit (IC) design. Some embodiments include burn-in testing the IC design using the workload...
8938695 Signature analytics for improving lithographic process of manufacturing semiconductor devices  
A number of wafers of a semiconductor device are inspected to generate a plurality of wafer inspection data. A method for identifying critical hot spots to improve lithographic process of...
8935644 Printed substrate design system, and printed substrate design method  
A printed substrate design system includes: an EMI condition determination unit that compares an EMI characteristic derived by an EMI characteristic derivation unit with an EMI allowable...
8935643 Parameter matching hotspot detection  
Disclosed are techniques for detecting hotspots using parameter matching. According to various implementations of the invention, devices in an electronic circuit design are classified into device...
8930865 Layout correcting method and layout correcting system  
A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of...
8930782 Root cause distribution determination based on layout aware scan diagnosis results  
Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a...
8930862 System, method, and computer program product for automatic two-phase clocking  
A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an...
8924904 Method and apparatus for determining factors for design consideration in yield analysis  
Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a...
8918988 Methods for controlling wafer curvature  
Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels,...
8918753 Correlation of device manufacturing defect data with device electrical test data  
Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For...
8914760 Electrical hotspot detection, analysis and correction  
Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device...
8914762 Automated generation of platform-specific logic designs for target environments from a common base design  
A method, computer-readable medium and apparatus for creating a platform-specific logic design from an input design are disclosed. For example, a method includes receiving an input design and an...
8912489 Defect removal process  
A process is provided for the removal of defects, for example, micro-bridging defects during device fabrication. In one aspect, a method includes: obtaining a wafer after lithography processing...
8910100 System and method for automatically reconfiguring chain of abutted devices in electronic circuit design  
The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected...
8910099 Method for debugging unreachable design targets detected by formal verification  
The present disclosure relates to a method for debugging in the formal verification of an integrated circuit design. The method may include providing, via a computing device, an electronic design...
8904326 Semiconductor device design method, system and computer program product  
In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least...
8904327 Assisting in logic circuit design to place cells on an IC substrate and optimize wiring  
A method of assisting in the design of a logic circuit enabling the placement and wiring of cells (logic operation elements) to be optimized on an IC substrate in a short period of time even when...
8904315 Circuit arrangements and associated apparatus and methods  
There is provided a method comprising: examining the location of one or more feature(s) of the one or more component(s) of a circuit arrangement to determine the displacement of the location of...
8904321 System and method for automatically generating coverage constructs and constraint solver distributions  
The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design and...
8904333 Mixed signal IP core prototyping system  
A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete...
8904328 Support apparatus and design support method  
A design support apparatus includes a detecting unit and a removing unit. The detecting unit detects a resistor whose terminals are open except one terminal and which has a resistance less than or...
8898607 Method and system for using a breadboard  
A method for using a breadboard involves receiving a circuit wiring connection layout, in which the circuit wiring connection layout includes a visual representation of circuit elements. The...