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9043736 Circuit design support method, computer product, and circuit design support apparatus  
A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output...
9038010 DRC format for stacked CMOS design  
The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer...
9038006 Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis  
A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes...
9038007 Prediction of dynamic current waveform and spectrum in a semiconductor device  
A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In...
9038008 System and method for containing analog verification IP  
A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog...
9032346 Method and apparatus for creating and managing waiver descriptions for design verification  
Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding...
9032345 Digital circuit verification monitor  
A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally...
9032350 Semiconductor device  
A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon...
9032339 Ranking verification results for root cause analysis  
Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of...
9032356 Programmable clock spreading  
An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated...
9032355 System and method for integrated transformer synthesis and optimization using constrained optimization problem  
A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design...
9032347 System and method for automated simulator assertion synthesis and digital equivalence checking  
A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user...
9032344 Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA  
A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs....
9026981 Dielectric reliability assessment for advanced semiconductors  
Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data...
9026968 Verification assistance for digital circuit designs  
To assist verification of a digital circuit design, a data processing system presents, within a graphical user interface of a display device, a presentation including a plurality of verification...
9026964 Intelligent metamodel integrated Verilog-AMS for fast and accurate analog block design exploration  
A method for modeling a circuit comprising storing a plurality of design variable ranges for a circuit component in a non-transient electronic data memory. Performing transistor-level simulations...
9026966 Co-simulation methodology to address performance and runtime challenges of gate level simulations with, SDF timing using emulators  
The present patent document relates to a method and apparatus for more efficiently simulating a circuit design (DUT), making use of a hardware functional verification device such as a...
9026979 Analysis support apparatus, analysis support method, and computer product  
An analysis support apparatus includes a processor that is configured to acquire circuit data that indicates plural elements within a circuit and a node to which at least two elements are...
9026963 System and method for fault sensitivity analysis of mixed-signal integrated circuit designs  
An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into...
9026962 Integrated electronic design automation system  
An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and...
9026965 Arrival edge usage in timing analysis  
A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing...
9026969 Method of designing arrangement of TSV in stacked semiconductor device and designing system for arrangement of TSV in stacked semiconductor device  
A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing...
9021409 Integration of data mining and static analysis for hardware design verification  
A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation...
9021412 RC extraction methodology for floating silicon substrate with TSV  
The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more...
9015643 System, method, and computer program product for applying a callback function to data values  
A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified....
9015012 Completion of partial coverage tasks  
A method, apparatus and product for completion of partial coverage tasks. The method comprising obtaining a partial coverage task defining a test with respect to a functional coverage model of a...
9009636 Analog circuit simulator and analog circuit verification method  
An analog circuit simulator includes a processor that is configured to search design data for analog circuits and an analog node connecting the analog circuits; collect variable information that...
9009638 Estimating transistor characteristics and tolerances for compact modeling  
Systems and methods for generating compact models that include the effects of physical and electrical variations independent of available hardware data. A method includes generating a...
9009640 Automatic computation of transfer functions  
Technologies pertaining to the automatic computation of transfer functions for a physical system are described herein. The physical system is one of an electrical system, a mechanical system, an...
9009635 System and method for simulator assertion synthesis and digital equivalence checking  
A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user...
9003343 Energy consumption simulation and evaluation system for embedded device  
An energy consumption simulation and evaluation system for embedded device in energy consumption evaluation technology for electronic devices, which solves the problem that the energy consumption...
9003339 Synthesis of clock gated circuit  
Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the...
8997034 Emulation-based functional qualification  
Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an...
8990746 Method for mutation coverage during formal verification  
The present disclosure relates to a method for formal verification of an integrated circuit design. The method may include providing an electronic design associated with the integrated circuit....
8990760 Cell-aware fault model generation for delay faults  
Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one...
8990745 Manipulation of traces for debugging behaviors of a circuit design  
A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value...
8990747 Logical Verification Apparatus and Method  
A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a...
8990744 Electrical measurement based circuit wiring layout modification method and system  
The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual...
8990743 Automated circuit design  
Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the...
8990739 Model-based retiming with functional equivalence constraints  
A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on...
8984457 System and method for a hybrid clock domain crossing verification  
A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural...
8984459 Methods and apparatus for layout verification  
Methods and apparatus of performing layout-versus-layout (LVL) comparison are disclosed. A layout may be in various formats such as GDSII or OASIS, for different circuits, and represented by a...
8977996 Method, design apparatus, and program product for incremental design space exploration  
A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a...
8977995 Timing budgeting of nested partitions for hierarchical integrated circuit designs  
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design...
8977994 Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints  
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level...
8977997 Hardware simulation controller, system and method for functional verification  
Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of...
8977998 Timing analysis with end-of-life pessimism removal  
A method for using computing equipment to perform timing analysis on an integrated circuit design includes identifying a timing arc of the integrated circuit design. The timing arc may be a clock...
8972915 Static timing analysis of template-based asynchronous circuits  
Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g.,...
8972785 Classifying processor testcases  
Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of...
8972914 Coexistence of multiple verification component types in a hardware verification framework  
Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open...