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8656376 Compiler for providing intrinsic supports for VLIW PAC processors with distributed register files and method thereof  
A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on...
8589634 Processor extensions for accelerating spectral band replication  
Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction...
8543794 Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements  
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of...
8543795 Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements  
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of...
8533431 Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements  
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of...
8255703 Atomic hash instruction  
A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to indicate whether the hash operation...
8132023 Apparatus and method for performing transparent hash functions  
A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash...
8132022 Apparatus and method for employing configurable hash algorithms  
A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of...
8117424 Systems, devices, and/or methods for managing programmable logic controller processing  
Certain exemplary embodiments can provide a programmable logic controller, which can comprise a Reduced Instruction Set Computer (RISC) processor. The RISC processor can be adapted to, responsive...
8112615 Single cycle reduced complexity CPU  
A single cycle RISC CPU. The single cycle RISC CPU includes an instruction decoder configured to perform an instruction fetch and an instruction decode. An arithmetic logic unit is coupled to the...
8060755 Apparatus and method for providing user-generated key schedule in a microprocessor cryptographic engine  
An apparatus and method for performing cryptographic operations within microprocessor. The apparatus includes an instruction register having a cryptographic instruction disposed therein, a keygen...
7971197 Automatic instruction set architecture generation  
A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations...
7921300 Apparatus and method for secure hash algorithm  
An x86-compatible microprocessor that executes an application program fetched from memory, including a single, atomic hash instruction directing the x86-compatible microprocessor to perform the...
7904645 Formatting disk drive data using format field elements  
Formatting disk drive data using format field elements (FFEs). A processing module (which can be a general purpose processor or a RISC (Reduced Instruction Set Computer) processor) is employed to...
7886131 Multithread processor with thread based throttling  
A multithreaded processor with dynamic thread based throttling, more specifically, based at least in part on the aggregated execution bandwidth requests of the threads, is disclosed herein. In...
7840789 Data hiding in compiled program binaries for supplementing computer functionality  
Bit reductions in program instructions are achieved by determining the set of bit patterns in bit locations of the instructions. If only a subset of bit patterns is present in the instructions,...
7685397 Apparatus and method for managing stacks in virtual machine  
An apparatus and method for managing stacks in a virtual machine are provided. The apparatus includes a first memory which checks the space of a stack chunk and allocates a frame pointer if at...
7620796 System and method for acceleration of streams of dependent instructions within a microprocessor  
A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a...
7478373 Kernel emulator for non-native program modules  
Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating...
7383425 Massively reduced instruction set processor  
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry...
7337443 Method and apparatus for processing program threads  
A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is...
7225436 Java hardware accelerator using microcode engine  
A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism...
7069423 Microcomputer  
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and...
7068394 Effects processor for compact printer  
An effects processor for an effects module. The effects processor comprises a RISC processor, a DSP for fast integer multiplication and a small memory. The processor uses VARK language and a...
6978233 Method for emulating multi-processor environment  
A method of and an apparatus for performing efficient software emulation of a multi-processor target computer by a host computer. The software technique permits multiple processors to be emulated...
6959375 High-performance, superscalar-based computer system with out-of-order instruction execution  
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality...
6957320 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
6948050 Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware  
A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit...
6938106 Network device interface for digitally interfacing data channels to a controller via a network  
The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a...
6915412 High-performance, superscalar-based computer system with out-of-order instruction execution  
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality...
6832306 Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions  
Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal...
6816750 System-on-a-chip  
A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus...
6779107 Computer execution by opportunistic adaptation  
A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality...
6766515 Distributed scheduling of parallel jobs with no kernel-to-kernel communication  
A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each...
6766438 RISC processor with a debug interface unit  
The present invention provides a RISC processor with a debug interface unit that enables the external replication of the data processing sequence within a RISC processor for debug purposes. The...
6735685 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
6728866 Partitioned issue queue and allocation strategy  
A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are...
6691305 Object code compression using different schemes for different instruction types  
A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a...
6654874 Microcomputer systems having compressed instruction processing capability and methods of operating same  
Microcomputer systems include an instruction processor therein that can process both normal length instructions and compressed instructions. The normal length instructions and the compressed...
6651159 Floating point register stack management for CISC  
A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose...
6615341 Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control  
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning...
6542981 Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode  
A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one...
6499100 Enhanced instruction decoding  
When decoding instructions of a program to be executed in a central processing unit comprising pipelining facilities for fast instruction decoding, part of the decoding is executed or the decoding...
6477636 Application-specific integrated circuit for processing defined sequences of assembler instructions  
The invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs). To improve data throughput in applications with high...
6425071 Subsystem bridge of AMBA's ASB bus to peripheral component interconnect (PCI) bus  
A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using...
6408376 Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously  
Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. The...
6385714 Data processing apparatus  
A data processing apparatus uses a stored-program method to execute an operation instructed by an instruction word that includes a register designation code as an operand. A plurality of work...
6349377 Processing device for executing virtual machine instructions that includes instruction refeeding means  
A processing device is disclosed that includes an instruction memory for storing virtual machine instructions, such as Java byte codes. A processor of the processing device includes a...
6349384 System, apparatus and method for processing instructions  
A data processing system comprises means for identifying and replacing instructions to jump to functions having known prolog instructions with modified jump instructions, means for storing the...
6330660 Method and apparatus for saturated multiplication and accumulation in an application specific signal processor  
An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation...

Matches 1 - 50 out of 158 1 2 3 4 >