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8909901 
Permute operations with flexible zero control
In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an... 

8904153 
Vector loads with multiple vector elements from a same cache line in a scattered load operation
Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of... 

8782376 
Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic
A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses... 

8688962 
Gather cache architecture
Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of... 

8683178 
Sharing a faultstatus register when processing vector instructions
The described embodiments provide a processor that executes vector instructions. In the described embodiments, the processor initializes an architectural faultstatus register (FSR) and a shadow... 

8667250 
Methods, apparatus, and instructions for converting vector data
A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and... 

8650382 
Load/move and duplicate instructions for a processor
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent... 

8649508 
System and method for implementing elliptic curve scalar multiplication in cryptography
A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further... 

8635431 
Vector gather buffer for multiple address vector loads
A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel... 

8375196 
Vector processor with vector register file configured as matrix of data cells each selecting input from generated vector data or data from other cell via predetermined rearrangement path
A data processing apparatus includes a vector register bank having a plurality of vector registers, each register including a plurality of storage cells, each cell storing a data element. A vector... 

8356159 
Break, prebreak, and remaining instructions for processing vectors
The described embodiments provide a system that sets elements in a result vector based on an input vector. During operation, the system determines a location of a key element within the input... 

8316215 
Vector processor with plural arithmetic units for processing a vector data string divided into plural register banks accessed by read pointers starting at different positions
It is an object to speed up a vector store instruction on a memory that is divided into banks as setting a plurality of elements as a unit while minimizing an increase in physical quantity. A... 

8255884 
Optimized scalar promotion with load and splat SIMD instructions
Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operationsplat operations may be determined based on an... 

8175853 
Systems and methods for a combined matrixvector and matrix transpose vector multiply for a blocksparse matrix
Systems and methods for combined matrixvector and matrixtranspose vector multiply for block sparse matrices. Exemplary embodiments include a method of updating a simulation of physical objects... 

8108652 
Vector processing with high execution throughput
The claimed invention is an efficient and highperformance vector processor. Through minimizing the use of multiple banks of memory and/or multiported memory blocks to reduce implementation cost,... 

8073881 
Methods and apparatus facilitating access to storage among multiple computers
Multiple computers in a cluster maintain respective sets of identifiers of neighbor computers in the cluster for each of multiple named resource. A combination of the respective sets of... 

7984273 
System and method for using a mask register to track progress of gathering elements from memory
A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where... 

7971036 
Methods and apparatus for attaching application specific functions within an array processor
A multinode video signal processor (VSPN) is describes that tightly couples multiple multicycle state machines (hardware assist units) to each processor and each memory in each node of an N node... 

7949853 
Two dimensional addressing of a matrixvector register array
A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B... 

7908460 
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a... 

7895379 
Logic controller having hardcoded control logic and programmable override control store entries
Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hardcoded logic to... 

7818539 
System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output... 

7809931 
Arrangement, system and method for vector permutation in singleinstruction multipledata mircoprocessors
A vector permutation system (100) for a singleinstruction multipledata microprocessor has a set of vector registers (110) which feed vectors to permutation logic (120) and then to a negate block... 

7793072 
Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands
A microprocessor including an execution unit enabled to execute an asymmetric instruction, where the asymmetric instruction includes a set of operand fields and an operation code (opcode). The... 

7793073 
Method and apparatus for indirectly addressed vector loadaddstore across multiprocessors
A method and apparatus to correctly compute a vectorgather, vectoroperate (e.g., vector add), and vectorscatter sequence, particularly when elements of the vector may be redundantly presented,... 

7788471 
Data processor and methods thereof
A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A... 

7743231 
Fast sparse list walker
Provided are a method, information processing system, and computer readable medium for identifying active bits in a vector. The method comprises receiving a pointer associated with a vector of... 

7739480 
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a... 

7725678 
Method and apparatus for producing an index vector for use in performing a vector permute operation
A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation... 

7610469 
Vector transfer system for packing discontiguous vector elements together into a single bus transfer
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the... 

7548248 
Method and apparatus for image blending
Methods and apparatuses for blending two images using vector table look up operations. In one aspect of the invention, a method to blend two images includes: loading a vector of keys into a vector... 

7519797 
Hierarchical multiprecision pipeline counters
An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is... 

7516299 
Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions
A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of... 

7496731 
Two dimensional addressing of a matrixvector register array
A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary... 

7467287 
Method and apparatus for vector table lookup
Methods and apparatuses for performing vector table lookup using multiple lookup tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a... 

7421565 
Method and apparatus for indirectly addressed vector loadadd store across multiprocessors
A method and apparatus to correctly compute a vectorgather, vectoroperate (e.g., vector add), and vectorscatter sequence, particularly when elements of the vector may be redundantly presented,... 

7404065 
Flow optimization and prediction for VSSE memory operations
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises... 

7366873 
Indirectly addressed vector loadoperatestore method and apparatus
A method and apparatus to correctly compute a vectorgather, vectoroperate (e.g., vector add), and vectorscatter sequence, particularly when elements of the vector may be redundantly presented,... 

7353371 
Circuit to extract nonadjacent bits from data packets
A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective... 

7350057 
Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction
Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for... 

7315932 
Data processing system having instruction specifiers for SIMD register operands and method thereof
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of... 

7293258 
Data processor and method for using a data processor with debug circuit
A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more... 

7254696 
Functionallevel instructionset computer architecture for processing applicationlayer contentservice requests such as fileaccess requests
A functionallevel instructionset computing (FLIC) architecture executes higherlevel functional instructions such as lookups and bitcompares of variablelength operands. Each FLIC... 

7219212 
Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one... 

7216218 
Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and... 

7206857 
Method and apparatus for a network processor having an architecture that supports burst writes and/or reads
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth... 

7200724 
Two dimensional data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second... 

7197625 
Alignment and ordering of vector elements for single instruction multiple data processing
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into... 

7111156 
Method and apparatus for multithread accumulation buffering in a computation engine
A method and apparatus for enhancing flexibility of instruction ordering in a multithread processing system that performs multiply and accumulate operations is presented. A plurality of... 

7107435 
System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register
A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary... 