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8862839 Storage system and storage management method for controlling off-line mode and on-line mode of flash memory  
A storage system which has flash memories constituting a storage area and a function of placing and handling the flash memories in on-line mode and off-line mode, and which stores and manages...
8856457 Information processing system and a system controller  
In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache...
8793689 Redundant multithreading processor  
A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant...
8418156 Two-stage commit (TSC) region for dynamic binary optimization in X86  
Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and...
8291503 Preloading modules for performance improvements  
Described is a technology for preloading modules, such as modules that show clinical/medical data maintained at a service, so as to reduce a user's wait time to use a module. The modules for which...
8209520 Expanded functionality of processor operations within a fixed width instruction encoding  
An apparatus for executing fixed width instructions in a multiple execution unit system has a device for fetching instructions from a memory, and a decoder for decoding each fetched instruction in...
7954114 Firmware socket module for FPGA-based pipeline processing  
A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module is configured to provide both commands and target data to an entry point in a data...
7782844 Method and apparatus for pattern matching on single and multiple pattern structures  
The present invention provides a method and apparatus for detecting and decoding data. The method comprises: receiving a set of data signals from an external data source; detecting a size of said...
7725698 Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor  
An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device...
7640418 Dynamic field patchable microarchitecture  
A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for...
7493478 Enhanced processor virtualization mechanism via saving and restoring soft processor/system states  
A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft...
7472051 Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor  
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
7447880 Processor with internal memory configuration  
A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory...
7418583 Data dependency detection using history table of entry number hashed from memory address  
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
7398376 Instructions for ordering execution in pipelined processes  
Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory...
7386710 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7191314 Reconfigurable CPU with second FSM control unit executing modifiable instructions  
A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set...
7124280 Execution control apparatus of data driven information processor for instruction inputs  
An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that...
7103759 Microcontroller architecture supporting microcode-implemented peripheral devices  
Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for...
7103758 Microcontroller performing safe recovery from standby mode  
A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is...
7000098 Passing a received packet for modifying pipelining processing engines' routine instructions  
In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program...
6986027 Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme  
This invention is a method and system for hybrid prediction of load addresses and/or values. The new scheme for value prediction provides prediction based on last values and strides, as well as...
6925554 Method of programming USB microcontrollers  
An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.
6920551 Configurable processor system  
A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset...
6915412 High-performance, superscalar-based computer system with out-of-order instruction execution  
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality...
6904511 Method and apparatus for register file port reduction in a multithreaded processor  
Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor...
6880074 In-line code suppression  
Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes...
6865669 Methods for optimizing memory resources during initialization routines of a computer system  
Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary...
6862676 Superscalar processor having content addressable memory structures for determining dependencies  
A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an...
6854051 Cycle count replication in a simultaneous and redundantly threaded processor  
A pipelined, simultaneous and redundantly threaded (“SRT”) processor comprising, among other components, load/store units configured to perform load and store operations to or from data locations...
6842848 Method and apparatus for token triggered multithreading  
Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled...
6820194 Method for reducing power when fetching instructions in a processor and related apparatus  
In one disclosed embodiment an instruction loop having at least one instruction is identified. For example, each instruction can be a VLIW packet comprised of several individual instructions. The...
6810477 Programmable controller including instruction decoder for judging execution/non-execution based on the state of contact points after execution of a preceding sequence program  
An instruction decode section judges execution/non-execution according to a state of a contact point of the last sequence program stored in a conductive/non-conductive information storage section...
6804772 Dynamic field patchable microarchitecture  
A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for...
6779102 Data processor capable of executing an instruction that makes a cache memory ineffective  
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the...
6772276 Flash memory command abstraction  
Flash memory device capable of interpreting a write cycle and one or more subsequent write cycles as a generic command that includes one or more specific flash memory commands. The flash memory...
6754807 System and method for managing vertical dependencies in a digital signal processor  
An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of...
6742107 Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data  
A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed....
6732258 IP relative addressing  
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
6725364 Configurable processor system  
A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset...
6708235 Multi-modem implementation with host based and digital signal processor based modems  
A plurality of modems or modem types can run on a host processor, a digital signal processor or both, either concurrently or selectively. Modules of more than one modem program can be swapped in...
6684323 Virtual condition codes  
The present invention utilizes a “virtual” condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal, non-architected...
6629192 Method and apparatus for use of a non-volatile storage management system for PC/AT compatible system firmware  
In one embodiment, the invention is an apparatus. The apparatus includes a BIOS embodied in a non-volatile storage device. The apparatus also includes a non-volatile storage manager embodied in...
6625725 Speculative reuse of code regions  
A speculative code reuse mechanism includes a reuse buffer, a main processing core and a reuse checking core. The reuse buffer includes inputs and outputs of previously executed instances of code...
6606704 Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode  
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
6574747 Extensible execute in place (XIP) architecture and related methods  
A system implementing an execute-in-place (XIP) architecture is presented comprising a plurality of XIP regions. To facilitate execute-in-place functionality across the multiple XIP regions, a...
6560698 Register change summary resource  
A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of...
6535984 Power reduction for multiple-instruction-word processors with proxy NOP instructions  
A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different...
6460129 Pipeline operation method and pipeline operation device to interlock the translation of instructions based on the operation of a non-pipeline operation unit  
A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the...

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