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8832419 |
Enhanced microcode address stack pointer manipulation
Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In some examples, the stacks are invisible to software. A microcode instruction pointer (UIP) and a... |
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8826261 |
Programming processors through CAN interface without changing the boot mode select pins
Methods, systems and devices for remotely updating software installed on a digital signal processor (DSP) without setting the mode select pins on the DSP control card. Firmware configured to... |
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8508782 |
Method of securing printers against malicious software
A method for securing a computer device against malicious code, the method including the steps of: executing a computer program on the computer device, the computer device having a central... |
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8447958 |
Substituting portion of template instruction parameter with selected virtual instruction parameter
A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to... |
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8423968 |
Template-based vertical microcode instruction trace generation
Method, system and computer program product for template-based vertical microcode instruction trace generation. An exemplary embodiment includes an instruction trace generation method, including... |
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8341383 |
Method and a system for accelerating procedure return sequences
A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a... |
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8171270 |
Asynchronous control transfer
Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is... |
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8145890 |
Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state
A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user... |
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8127120 |
Secured processing unit
A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the... |
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8037285 |
Trace unit
An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of... |
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7694110 |
System and method of implementing microcode operations as subroutines
Various embodiments of methods and systems for implementing a set of microcode operations corresponding to a microcoded instruction as a microcode subroutine are disclosed. In one embodiment, a... |
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7617388 |
Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at... |
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7613907 |
Embedded software camouflage against code reverse engineering
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will... |
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7574587 |
Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics
A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a... |
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7529914 |
Method and apparatus for speculative execution of uncontended lock instructions
A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will... |
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7526638 |
Hardware alteration of instructions in a microcode routine
Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a... |
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7444501 |
Methods and apparatus for recognizing a subroutine call
An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a... |
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7412593 |
Processor for processing a program with commands including a mother program and a sub-program
A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump... |
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7398372 |
Fusing load and alu operations
Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a... |
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7392370 |
Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics
A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a... |
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7383425 |
Massively reduced instruction set processor
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry... |
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7237098 |
Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address.... |
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7231511 |
Microinstruction pointer stack including speculative pointers for out-of-order execution
Methods and apparatus, including computer program products, for a microinstruction pointer stack in a processor. A method executed in a processor includes executing microcode (μcode) addressed by... |
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7219218 |
Vector technique for addressing helper instruction groups associated with complex instructions
The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply,... |
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7203826 |
Method and apparatus for managing a return stack
A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels... |
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7162621 |
Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at... |
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7127718 |
Multitasking microcontroller for controlling the physical layer of a network interface card and method of operation
There is disclosed an apparatus for controlling a physical layer interface of a network interface card in real time. The apparatus comprises: 1) a first memory for storing a multitasking control... |
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7069424 |
Placing front instruction in replay loop to front to place side instruction into execution stream upon determination of criticality
A method and apparatus for whacking a μOP based upon the criticality of that μOP. Also disclosed are embodiments of a method for determining the criticality of a μOP. |
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7055022 |
Paired load-branch operation for indirect near jumps
A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation... |
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7039793 |
Microprocessor apparatus and method for accelerating execution of repeat string instructions
A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup... |
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7035999 |
Register window fill technique for retirement window having entry size less than amount of fill instructions
A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill... |
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7024541 |
Register window spill technique for retirement window having entry size less than amount of spill instructions
A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill... |
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6957319 |
Integrated circuit with multiple microcode ROMs
Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same... |
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6957322 |
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion
A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to... |
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6898699 |
Return address stack including speculative return address buffer with back pointers
An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative... |
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6865669 |
Methods for optimizing memory resources during initialization routines of a computer system
Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary... |
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6857063 |
Data processor and method of operation
A data processor executes an instruction (JAVASW) to implement efficient interpreter functionality by combining the tasks of table jumps and thread or task switching which is controlled by a... |
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6842842 |
Method and system to preprogram and predict a next microcode address
A microprocessor includes a first memory to store microcode and a second memory to store predicted micro-operation addresses. Micro-operation addresses are predicted, stored in memory, and... |
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6807626 |
Execution of a computer program
A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the... |
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6718414 |
Function modification in a write-protected operating system
An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of... |
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6697938 |
Microcomputer executing an ordinary branch instruction and a special branch instruction
A microcomputer has a built-in memory and is accessible to an external memory. The microcomputer executes a specific area branch instruction “JM” as an executable instruction. The specific area... |
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6625726 |
Method and apparatus for fault handling in computer systems
A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first... |
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6609191 |
Method and apparatus for speculative microinstruction pairing
An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro... |
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6578139 |
Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in... |
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6542981 |
Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode
A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one... |
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6519696 |
Paired register exchange using renaming register map
An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of... |
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6499067 |
Serial communication apparatus and serial communication system
A serial communication system, which can improve a communication speed even when it takes long time to perform a process in accordance with a command. A serial communication apparatus includes a... |
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6477636 |
Application-specific integrated circuit for processing defined sequences of assembler instructions
The invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs). To improve data throughput in applications with high... |
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6470493 |
Computer method and apparatus for safe instrumentation of reverse executable program modules
Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention... |
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6446196 |
Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications
A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of... |