Matches 1 - 50 out of 350 1 2 3 4 5 6 7 >


Match Document Document Title
9038074 System, method and computer program product for recursively executing a process control operation to use an ordered list of tags to initiate corresponding functional operations  
In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map...
9026769 Detecting and reissuing of loop instructions in reorder structure  
A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded...
8892853 Hardware to support looping code in an image processing system  
An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor...
8869129 Apparatus and method for scheduling instruction  
An apparatus and method for scheduling an instruction are provided. The apparatus includes an analyzer configured to analyze dependency of a plurality of recurrence loops and a scheduler...
8856499 Reducing instruction execution passes of data groups through a data operation unit  
An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with...
8850170 Apparatus and method for dynamically determining execution mode of reconfigurable array  
An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution...
8850171 Multithreaded parallel execution device, broadcast stream playback device, broadcast stream storage device, stored stream playback device, stored stream re-encoding device, integrated circuit, multithreaded parallel execution method, and multithreaded compiler  
When a temporary data storage unit 104 stores a value of “3” and an iteration number of “3”, and a data updating management unit 103 receives a value of “2” in combination with an iteration number...
8806184 Branch prediction method and branch prediction circuit performing the method  
A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the...
8799629 Parallel execution of a loop  
A method of executing a loop over an integer index range of indices in a parallel manner includes assigning a plurality of index subsets of the integer index range to a corresponding plurality of...
8762126 Analyzing simulated operation of a computer  
Analyzing simulated operation of a computer including loading user-defined dynamically linked analysis libraries that each include specifications of events to be traced for analysis, including:...
8756406 Method and apparatus for programmable coupling between CPU and co-processor  
In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution...
8726238 Interactive iterative program parallelization based on dynamic feedback  
Interactive iterative program parallelization based on dynamic feedback program parallelization, in one aspect, may identify a ranked list of one or more candidate pieces of code each with one or...
8713293 Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture  
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a...
8707424 Method for making secure execution of a computer programme, in particular in a smart card  
A method for making secure execution of a computer program includes the following steps: stacking a predetermined value in a pile of instructions of the program; and stack popping the pile, the...
8683185 Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set  
The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a...
8683178 Sharing a fault-status register when processing vector instructions  
The described embodiments provide a processor that executes vector instructions. In the described embodiments, the processor initializes an architectural fault-status register (FSR) and a shadow...
8667260 Building approximate data dependences with a moving window  
Mechanisms for building approximate data dependences using a moving look-back window are provided. The mechanisms track dependence information for memory accesses over iterations of execution of a...
8612732 Retargetting an application program for execution by a general purpose processor  
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit...
8595474 Information processing apparatus and branch prediction method  
An information processor includes a first recording unit which stores first information indicating correspondence between an instruction address and a branch destination address of a most recent...
8595745 Job-process swapping between multiple storage devices based on the most recently executed type of a process and historical execution count among plural types of processes  
A memory swap management method that can preferentially place in a primary storage device a process that has a high possibility of being executed next, thereby shortening the time to start...
8589666 Elimination of stream consumer loop overshoot effects  
A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain...
8583905 Runtime extraction of data parallelism  
Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group...
8578141 Loop predictor and method for instruction fetching using a loop predictor  
A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in...
8572359 Runtime extraction of data parallelism  
Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group...
8539211 Allocating registers for loop variables in a multi-threaded processor  
A multi-threaded processor comprises a processing unit (PU) for concurrently processing multiple threads. A register file means (RF) is provided having a plurality of registers, wherein a first...
8527743 Simultaneous checking of plural exit conditions loaded in table subsequent to execution of wait instruction for jitter free exit  
A microprogrammable electronic device comprises a code memory storing a plurality of instructions. At least one instruction, when executed by the device, causes the device to enter into a wait...
8520016 Instruction folding mechanism, method for performing the same and pixel processing system employing the same  
An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel...
8495345 Computing apparatus and method of handling interrupt  
A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt...
8447961 Mechanism for efficient implementation of software pipelined loops in VLIW processors  
A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a...
8438370 Processing of loops with internal data dependencies using a parallel processor  
Loops with internal data dependencies (e.g., in a Mersenne Twister pseudorandom number generator) are implemented by exploiting arrays of cooperating threads that can be executed concurrently...
8387036 Method and system for execution profiling using loop count variance  
A method for executing a computer program involving obtaining a statement of the source code, where the statement comprises a method call, and where the source code is composed in a...
8359462 Method and apparatus for programmable coupling between CPU and co-processor  
In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution...
8352686 Method and system for data prefetching for loops based on linear induction expressions  
An efficient and effective compiler data prefetching technique is disclosed in which memory accesses may be prefetched are represented in linear induction expressions. Furthermore, indirect memory...
8296750 Optimization of a target program  
A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information...
8266414 Method for executing an instruction loop and a device having instruction loop execution capabilities  
A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a...
8266410 Meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors  
In an implementation, a processing system includes an instruction fetch (IF) memory storing IF instructions; an arithmetic/logic (AL) instruction memory (IMemory) storing instructions; and a...
8225077 Obfuscation device for generating a set of obfuscated instructions, processing device, method, program, and integrated circuit thereof  
An obfuscation device includes a first instruction generating unit, for each of a first process and a second process, which generates an initialization instruction for securing a management area...
8209525 Method and apparatus for executing program code  
The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control...
8191057 Systems, methods, and computer products for compiler support for aggressive safe load speculation  
Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a...
8171464 Efficient code generation using loop peeling for SIMD loop code with multile misaligned statements  
An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if...
8134411 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop  
A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a...
8131979 Check-hazard instructions for processing vectors  
The described embodiments provide a system that determines data dependencies between two vector memory operations or two memory operations that use vectors of memory addresses. During operation,...
8122239 Method and apparatus for initializing a system configured in a programmable logic device  
Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with...
8058896 Flexible parallel/serial reconfigurable array configuration scheme  
A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection...
8055886 Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction  
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a...
8019982 Loop data processing system and method for dividing a loop into phases  
A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing...
8019981 Loop instruction execution using a register identifier  
Methods and apparatus are provided for performing loop execution. Modifier registers are used to hold loop counter values. Modifier register information and program memory address information are...
8015391 Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop  
A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple...
7996661 Loop processing counter with automatic start time set or trigger modes in context reconfigurable PE array  
A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the...
7991985 System and method for implementing and utilizing a zero overhead loop  
Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism,...

Matches 1 - 50 out of 350 1 2 3 4 5 6 7 >