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9043773 Identification and management of unsafe optimizations  
Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a...
9037835 Data processing method and apparatus for prefetching  
A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a...
9021241 Combined branch target and predicate prediction for instruction blocks  
Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and...
9020616 Control apparatus and control method of performing operation control of actuators  
In a microcomputer, by virtue of the function of one input signal judgment module in the application layer, with respect to whether the situation is such that operation is to be requested to a...
9015720 Efficient state transition among multiple programs on multi-threaded processors by executing cache priming program  
A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or...
9009734 Application level speculative processing  
One or more embodiments of the invention is a computer-implemented method for speculatively executing application event responses. The method includes the steps of identifying one or more event...
8978022 Reducing instruction miss penalties in applications  
Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to...
8886920 Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage  
A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support...
8832384 Reassembling abstracted memory accesses for prefetching  
A storage proxy receives different abstracted memory access requests that are abstracted from the original memory access requests from different sources. The storage proxy reconstructs the...
8725992 Programming language exposing idiom calls to a programming idiom accelerator  
A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the...
8694759 Generating predicted branch target address from two entries storing portions of target address based on static/dynamic indicator of branch instruction type  
A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes...
8667257 Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit  
Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to...
8650364 Processing system with linked-list based prefetch buffer and methods for use therewith  
A processing device includes a memory and a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to...
8607209 Energy-focused compiler-assisted branch prediction  
A processor framework includes a compiler to add control information to an instruction sequence at compile time. The control information is added in the instruction sequence prior to a...
8578134 System and method for aligning change-of-flow instructions in an instruction buffer  
A method and processor are provided. The method includes storing a first value at a first field of a first cache tag line when a next occurrence of a first COF instruction is presumed to branch...
8566568 Method and apparatus for executing processor instructions based on a dynamically alterable delay  
Instruction execution delay is alterable after the system design has been finalized, thus enabling the system to dynamically account for various conditions that impact instruction execution. In...
8543767 Prefetching with multiple processors and threads via a coherency bus  
A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a...
8539501 Managing access to a shared resource in a data processing system  
Processes requiring access to shared resources are adapted to issue a reservation request, such that a place in a resource access queue, such as one administered by means of a semaphore system,...
8533399 Cache directory look-up re-use as conflict check mechanism for speculative memory requests  
In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of...
8533721 Method and system of scheduling out-of-order operations without the requirement to execute compare, ready and pick logic in a single cycle  
A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling...
8522250 Managing access to a shared resource in a data processing system  
Processes requiring access to shared resources are adapted to issue a reservation request, such that a place in a resource access queue, such as one administered by means of a semaphore system,...
8443176 Method, system, and computer program product for reducing cache memory pollution  
A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching...
8392893 Emulation method and computer system  
The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of...
8387053 Method and system for enhancing computer processing performance  
A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled...
8341635 Hardware wake-and-go mechanism with look-ahead polling  
A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in a thread for programming idioms that indicates that the thread is waiting for an...
8271750 Entry replacement within a data store using entry profile data and runtime performance gain data  
A data processing system includes a data store having storage locations storing entries which can be used for a variety of purposes, such as operand value prediction, branch prediction, etc. An...
8200905 Effective prefetching with multiple processors and threads  
A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a...
8141098 Context switch data prefetching in multithreaded computer  
An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known...
8078806 Microprocessor with improved data stream prefetching  
A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch...
8069270 Accelerated tape backup restoration  
According to the present invention, methods and apparatus are provided improving reading of a remote tape device by a host through multiple fibre channel switches. A fibre channel switch...
7984279 System and method for using a working global history register  
A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline...
7925870 Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch  
An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The...
7913255 Background thread processing in a multithread digital signal processor  
Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide background...
7900019 Data access target predictions in a data processing system  
A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address...
7877580 Branch lookahead prefetch for microprocessors  
A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during...
7836288 Branch prediction mechanism including a branch prediction memory and a branch prediction cache  
A data processing system 2 incorporating an instruction pipeline 14 and a prefetch unit 16 is provided with a branch prediction mechanism using both a branch prediction memory 20 storing 1-bit...
7822943 Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs)  
Systems, methods and computer program products for improving data stream prefetching in a microprocessor are described herein. The method includes the steps of: 1) translating an address...
7814469 Speculative multi-threading for instruction prefetch and/or trace pre-build  
The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread...
7814247 Pre-fetch circuit of semiconductor memory apparatus and control method of the same  
A pre-fetch circuit of a semiconductor memory apparatus can carry out a high-frequency operating test through a low-frequency channel of a test equipment. The pre-fetch circuit of a semiconductor...
7809547 Host computer system emulating target system legacy software and providing for incorporating more powerful application program elements into the flow of the legacy software  
As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating...
7797520 Early branch instruction prediction  
A data processing apparatus including a prefetch unit for prefetching the instructions from a memory, branch prediction logic and a branch target cache for storing predetermined information about...
7793085 Memory control circuit and microprocessory system for pre-fetching instructions  
A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination...
7783869 Accessing branch predictions ahead of instruction fetching  
A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from...
7783868 Instruction fetch control device and method thereof with dynamic configuration of instruction buffers  
This is an instruction fetch control device supplying instructions to an instruction execution unit. The device comprises a plurality of instruction buffers storing an instruction string to be...
7783870 Branch target address cache  
A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that...
7774766 Method and system for performing reassociation in software loops  
Various embodiments of the present invention relate to methods and systems for optimizing an intermediate code in a compilation logic. The intermediate code is optimized by performing...
7734901 Processor core and method for managing program counter redirection in an out-of-order processor pipeline  
A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction...
7721048 System and method for cache replacement  
A computer processing system is disclosed that includes a cache that includes cache blocks of data. The system includes a marking sub-system, an ordering sub-system, and a replacement sub-system....
7712091 Method for predicate promotion in a software loop  
A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a...
7702888 Branch predictor directed prefetch  
An apparatus for executing branch predictor directed prefetch operations. During operation, a branch prediction unit may provide an address of a first instruction to the fetch unit. The fetch unit...

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