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9003160 Active buffered memory  
According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command...
8977815 Control of entry of program instructions to a fetch stage within a processing pipepline  
A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation...
8966228 Instruction fetching following changes in program flow  
This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an...
8954714 Processor with cycle offsets and delay lines to allow scheduling of instructions through time  
An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than...
8930677 Computer operation control method, program, and system  
A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object...
8918622 Computer operation control method, program and system  
A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object...
8909902 Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution  
Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A...
8898434 Optimizing system throughput by automatically altering thread co-execution based on operating system directives  
A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program...
8898435 Optimizing system throughput by automatically altering thread co-execution based on operating system directives  
A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program...
8832464 Processor and method for implementing instruction support for hash algorithms  
A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The...
8832414 Dynamically determining the profitability of direct fetching in a multicore architecture  
Technologies are generally described herein for determining a profitability of direct fetching in a multicore processor. The multicore processor may include a first and a second tile. The first...
8812169 Heat sink verification  
In one embodiment, a printed circuit board assembly comprises a printed circuit board including a processor, a heat sink mountable to the printed circuit board proximate the processor, and a...
8769539 Scheduling scheme for load/store operations  
A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a...
8719589 Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values  
A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS...
8700887 Register, processor, and method of controlling a processor using data type information  
A processor and a processor control method which efficiently perform an operation on data using a register, are provided. The register may include a data type field and a data field. The processor...
8669990 Sharing resources between a CPU and GPU  
A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring...
8661228 Multi-level register file supporting multiple threads  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
8661227 Multi-level register file supporting multiple threads  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
8650385 Instruction fetch apparatus, processor and program counter addition control method  
An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8639945 Branch and switch key instruction in a microprocessor that fetches and decrypts encrypted instructions  
A microprocessor includes a storage element that stores decryption key data and a fetch unit that fetches and decrypts program instructions using a value of the decryption key data stored in the...
8635437 Pipelined microprocessor with fast conditional branch instructions based on static exception state  
A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a...
8624916 Processing global atomic operations using the bending unit datapath  
One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the...
8624910 Register indexed sampler for texture opcodes  
One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value...
8624906 Method and system for non stalling pipeline instruction fetching from memory  
A method and system for graphics instruction fetching. The method includes executing a plurality of threads in a multithreaded execution environment. A respective plurality of instructions are...
8615644 Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition  
A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily...
8564604 Systems and methods for improving throughput of a graphics processing unit  
Systems and methods for improving throughput of a graphics processing unit are disclosed. In one embodiment, a system includes a multithreaded execution unit capable of processing requests to...
8549255 Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system  
A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a...
8538572 Methods for constructing an optimal endpoint algorithm  
A method for automatically identifying an optimal endpoint algorithm for qualifying a process endpoint during substrate processing within a plasma processing system is provided. The method...
8539190 Preemptive in-pipeline store compare resolution  
A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having...
8526257 Processor with memory delayed bit line precharging  
A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate...
8516225 Central processing unit and microcontroller  
A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each...
8495643 Message selection based on time stamp and priority in a multithreaded processor  
A method and circuit arrangement process a workload in a multithreaded processor that includes a plurality of hardware threads. Each thread receives at least one message carrying data to process...
8478966 Query sampling information instruction  
A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the...
8467175 System and method for an optimizable rack solution  
In accordance with the present disclosure, a system and method for an optimizable rack solution is presented. The system and method is directed to an optimizable rack that includes a frame. The...
8468324 Dual thread processor  
Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter...
8464028 Redirection table and predictor for fetching instruction routines in a virtual machine guest  
In one embodiment, a processor comprises a redirect unit configured to detect a match of an instruction pointer (IP) in an IP redirect table, the IP corresponding to a guest instruction that the...
8453161 Method and apparatus for efficient helper thread state initialization using inter-thread register copy  
This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated...
8443168 Microcontroller comprising a plurality of registers and instruction modes  
A microcontroller includes a plurality of primary registers, a secondary register and a central processing unit (CPU). The primary registers store a plurality of primary data respectively. Each...
8427952 Microcode engine for packet processing  
Apparatus and methods to efficiently process packet data are disclosed. In one embodiment, a microcode engine designed to efficiently parse packet data may use instructions that are tailored to...
8411103 Processing global atomic operations using the bending unit datapath  
One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the...
8413127 Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations  
A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and...
8407442 Preemptive in-pipeline store compare resolution  
A computer-program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The...
8397031 Apparatus, processor and method of cache coherency control  
An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period...
8392663 Coherent instruction cache utilizing cache-op execution resources  
A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance...
8392666 Low power high speed load-store collision detector  
An apparatus detects a load-store collision within a microprocessor between a load operation and an older store operation each of which accesses data in the same cache line. Load and store byte...
8387053 Method and system for enhancing computer processing performance  
A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled...
8364935 Data processing apparatus address range dependent parallelization of instructions  
A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of...
8346760 Method and apparatus to improve execution of a stored program  
In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata.
8321861 Non-native program execution across multiple execution environments  
A data processing system 2 executes non-native program instructions using either a first execution environment 14 or a second execution environment 22. The first execution environment identifies...

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