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9032174 Information processing apparatus for restricting access to memory area of first program from second program  
A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so...
9019957 Network telephony system  
The present invention includes a network telephone having a microphone coupled to provide voice data to a network, a speaker coupled to facilitate listening to voice data from the network, a...
9003274 Scheduling start-up and shut-down of mainframe applications using topographical relationships  
The illustrative embodiments provide for a system and recordable type medium for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and...
8984256 Thread optimized multiprocessor architecture  
In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the...
8977836 Thread optimized multiprocessor architecture  
In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the...
8977800 Multi-port cache memory apparatus and method  
Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate...
8972674 Compensation for solid state storage  
A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration...
8959304 Management of data processing security in a secondary processor  
A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory...
8886915 Multiprocessor system having direct transfer function for program status information in multilink architecture  
A multiprocessor system can directly transmit storage-state information in a multilink architecture. The multiprocessor system includes a first processor; a multiport semiconductor memory device...
8856457 Information processing system and a system controller  
In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache...
8812824 Method and apparatus for employing multi-bit register file cells and SMT thread groups  
There are provided methods and apparatus for multi-bit cell and SMT thread groups. An apparatus for a register file includes a plurality of multi-bit storage cells for storing a plurality of bits...
8656141 Architecture and programming in a parallel processing environment with switch-interconnected processors  
An integrated circuit includes a plurality of tiles. Each tile includes a pipelined processor configured to process multiple streams of instructions for the processor; and a switch including...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8601176 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
8595466 All-to-all comparisons on architectures having limited storage space  
Mechanisms for performing all-to-all comparisons on architectures having limited storage space are provided. The mechanisms determine a number of data elements to be included in each set of data...
8532288 Selectively isolating processor elements into subsets of processor elements  
A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks...
8464025 Signal processing apparatus with signal control units and processor units operating based on different threads  
A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203ā€”0 to 203ā€”3 access data at an...
8458532 Error handling mechanism for a tag memory within coherency control circuitry  
A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data...
8447957 Coprocessor interface architecture and methods of operating the same  
A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a...
8250338 Broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing  
A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control...
8244931 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
8214618 Memory management method, medium, and apparatus based on access time in multi-core system  
A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a...
8190855 Coupling data for interrupt processing in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
8127111 Managing data provided to switches in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
8112612 Processing system with interspersed processors using selective data transfer through communication elements  
A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one...
8082372 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
8065681 Generic shared memory barrier  
A method, information processing node, and a computer program storage product are provided for performing synchronization operations between participants of a program. Each participant includes at...
7975080 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
7908020 Architecture for control systems  
An architecture for control systems including multiple control devices. The control devices include standardized software objects having functions, application programs for engaging these...
7908603 Intelligent memory with multitask controller and memory partitions storing task state information for processing tasks interfaced from host processor  
The disclosure describes a computing system having one or more processing elements, one of which is a floating point processor, a memory, and a multitask controller. The multitask controller...
7900014 Memory request/grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system  
A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of...
7895412 Programmable arrayed processing engine architecture for a network switch  
A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed...
7765338 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
7734894 Managing data forwarded between processors in a parallel processing environment based on operations associated with instructions issued by the processors  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
7694151 Architecture, system, and method for operating on encrypted and/or hidden information  
An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to...
7664928 Method and apparatus for providing user-defined interfaces for a configurable processor  
A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These...
7636835 Coupling data in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
7584332 Computer systems with lightweight multi-threaded architectures  
Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.
7581079 Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions  
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also...
7539845 Coupling integrated circuits in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
7519793 Facilitating inter-DSP data communications  
A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate...
7503046 Method of obtaining interleave interval for two data values  
A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2zāˆ’n may be used to represent the value of y, includes...
7493468 Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing  
A method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control...
7461236 Transferring data in a parallel processing environment  
An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor...
7451292 Methods for transmitting data across quantum interfaces and quantum gates using same  
Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision,...
7428629 Memory request / grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system  
A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of...
7409529 Method and apparatus for a shift register based interconnection for a massively parallel processor array  
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still...
7409528 Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof  
A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7398368 Atomic operation involving processors with different memory transfer operation sizes  
Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that...

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