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9043802 Adjustment of threads for execution based on over-utilization of a domain in a multi-processor system by destroying parallizable group of threads in sub-domains  
Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each...
9037833 High performance computing (HPC) node having a plurality of switch coupled processors  
A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job,...
9038073 Data mover moving data to accelerator for processing and returning result data based on instruction received from a processor utilizing software and hardware interrupts  
Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final...
8904148 Processor architecture with switch matrices for transferring data along buses  
There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to...
8898432 Folded SIMD array organized in groups (PEGs) of respective array segments, control signal distribution logic, and local memory  
Systems and methods for folding a single instruction multiple data (SIMD) array include a newly defined processing element group (PEG) that allows interconnection of PEGs by abutment without...
8892806 Integrated circuit, memory device, method of operating an integrated circuit, and method of designing an integrated circuit  
An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of...
8830829 Parallel processing using multi-core processor  
Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of...
8832413 Processing system with interspersed processors and communication elements having improved wormhole routing  
A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through...
8825924 Asynchronous computer communication  
A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner...
8826228 Programming a multi-processor system  
A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a...
8812820 Data processing device and method  
A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other...
8768642 System and method for remotely configuring semiconductor functional circuits  
The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional...
8745604 Transferring data in a parallel processing environment  
An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to...
8737392 Configuring routing in mesh networks  
A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the...
8667251 Electronic chip and integrated circuit including a split routing unit having first-level routers for intra-layer transmissions and second-level routers for inter-layer transmissions and transmissions to the processing units  
This electronic chip includes functional modules each including a single processing unit and a single routing unit (110E) connected to one another, and connections, called routing connections,...
8667049 Massively parallel supercomputer  
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application...
8656141 Architecture and programming in a parallel processing environment with switch-interconnected processors  
An integrated circuit includes a plurality of tiles. Each tile includes a pipelined processor configured to process multiple streams of instructions for the processor; and a switch including...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8631415 Adjustment of threads for execution based on over-utilization of a domain in a multi-processor system by sub-dividing parallizable group of threads to sub-domains  
Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each...
8625422 Parallel processing using multi-core processor  
Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of...
8612507 Computing device, calculating method, and program product  
A computing device includes: a deciding unit which, in computation of values of nodes on a lattice in a direction where a value of m representing a horizontal axis coordinate of the lattice...
8607029 Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network  
A dynamic reconfigurable circuit including a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port, a data network...
8601176 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
8583896 Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain  
Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to...
8549257 Area efficient arrangement of interface devices within an integrated circuit  
An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of...
8532288 Selectively isolating processor elements into subsets of processor elements  
A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks...
8516179 Integrated circuit with coupled processing cores  
A processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or...
8510535 Mixed torus and hypercube multi-rank tensor expansion method  
The present invention provides a mixed torus and hypercube multi-rank tensor expansion method which can be applied to the communication subsystem of a parallel processing system. The said...
8490110 Network on chip with a low latency, high bandwidth application messaging interconnect  
Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block...
8490066 Profiler for optimizing processor architecture and application  
A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which...
8484444 Methods and apparatus for attaching application specific functions within an array processor  
A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node...
8484276 Processing array data on SIMD multi-core processor architectures  
Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor...
8478967 Automatically creating parallel iterative program code in a data flow program  
System and method for automatically parallelizing iterative functionality in a data flow program. A data flow program is stored that includes a first data flow program portion, where the first...
8464025 Signal processing apparatus with signal control units and processor units operating based on different threads  
A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an...
8453003 Communication method  
A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each...
8447803 Method and apparatus for distributing network traffic processing on a multiprocessor computer  
An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol...
8443169 Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor  
A Wings array system for communicating between nodes using store and load instructions is described. Couplings between nodes are made according to a 1 to N adjacency of connections in each...
8438512 Method and system for implementing efficient locking to facilitate parallel processing of IC designs  
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout...
8429382 Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology  
A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk....
8417917 Processor core stacking for efficient collaboration  
A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary...
8375395 Switch-based parallel distributed cache architecture for memory access on reconfigurable computing platforms  
A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a...
8370844 Mechanism for process migration on a massively parallel computer  
Embodiments off the invention provide a mechanism for process migration on a massively parallel computer system. In particular, embodiments of the invention may be used to update process state...
8327114 Matrix processor proxy systems and methods  
In some embodiments, processor-to-processor and/or broadcast proxies are designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default...
8307116 Scalable bus-based on-chip interconnection networks  
The present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical...
8276116 Algebra operation method, apparatus, and storage medium thereof  
An algebra operation method includes the steps of converting algebra operations for a plurality of objects which appear in a program into an algebra operation sequence object described using...
8253753 Dual-type component connections  
Component connections are preserved during destructive component operations. Upon receiving a notification of the destruction of a direct component connection, a direct component connection is...
8250337 Array processor with two parallel processing paths of multipliers and ALUs with idle operation capability controlled by portions of opcode including indication of valid output  
General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as...
8244931 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
8225073 Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements  
The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a...
8200940 Reduction operations in a synchronous parallel thread processing system with disabled execution threads  
A system and method for successfully performing reduction operations in a multi-threaded SIMD (single-instruction multiple-data) system while one or more threads are disabled allows for the...

Matches 1 - 50 out of 450 1 2 3 4 5 6 7 8 9 >