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9009441 |
Memory channel selection in a multi-channel memory
In general, this disclosure describes techniques for selecting a memory channel in a multi-channel memory system for storing data, so that usage of the memory channels is well-balanced. A request... |
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8943297 |
Parallel read functional unit for microprocessors
A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and... |
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8914612 |
Data processing with time-based memory access
Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available... |
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8880808 |
Centralized memory allocation with write pointer drift correction
A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data... |
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8880815 |
Low access time indirect memory accesses
An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second... |
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8880796 |
Seamlessly stitching a user data set from multiple memories
An apparatus and associated methodology providing a data storage system including a memory having a first addressable storage space and a second differently addressable storage space. A controller... |
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8812819 |
Methods and apparatus for reordering data signals in fast fourier transform systems
Data signal items output by a radix 4n2m fast Fourier transform (“FFT”) operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural... |
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8762686 |
Multimode accessible storage facility
A multimode accessible storage facility (10) is described that allows block access in a block access mode and row access in a row access mode. The facility comprises—a memory unit (20) comprising... |
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8688761 |
Arithmetic logic and shifting device for use in a processor
An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a... |
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8671261 |
Lightweight random memory allocation
In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A... |
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8635426 |
Diagonally accessed memory array circuit
A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by... |
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8527802 |
Memory device data latency circuits and methods
A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of... |
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8510503 |
Ring buffer circuit and control circuit for ring buffer circuit
Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or... |
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8473693 |
Managing ownership of memory buffers (mbufs)
The present invention provides techniques for managing ownership (i.e., control) of one or more memory buffer (mbuf) data structures within a network subsystem and a storage subsystem of a storage... |
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8364930 |
Information processing apparatus and storage drive adapted to perform fault analysis by maintenance of tracing information
According to one embodiment, an information processing apparatus includes an information processing apparatus main body and a storage drive which is accommodated in the information processing... |
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8352708 |
Parallel read functional unit for microprocessors
A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software... |
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8321649 |
Memory controller address and data pin multiplexing
A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each... |
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8275934 |
Nonvolatile memory device and cache read method using the same
A nonvolatile memory device includes first and second registers configured to store parameters received via an input/output (IO) unit, a microcontroller configured to control an operation of the... |
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8254204 |
Burst address generator and test apparatus including the same
A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the... |
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8255668 |
Interface, memory system, and access control method
An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of... |
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8239658 |
Internally derived address generation system and method for burst loading of a synchronous memory
An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an... |
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8233780 |
Reproducing apparatus and method, and recording medium
A reproducing apparatus and method includes a reproducing unit to reproduce mainstream data and sub audio data separately added in the mainstream data, wherein the reproducing unit comprises a... |
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8195919 |
Handling multi-cycle integer operations for a multi-threaded processor
Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented... |
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8171258 |
Address generation unit with pseudo sum to accelerate load/store operations
In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the... |
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8166278 |
Hashing and serial decoding techniques
A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and... |
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8099448 |
Arithmetic logic and shifting device for use in a processor
An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a... |
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8051272 |
Method and system for generating addresses for a processor
A method for generating addresses for a processor is provided. The addresses are for use by an application that may be executed by the processor. The application comprises a plurality of... |
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8028149 |
Method of reading the memory plane of a contactless tag
A method of reading a group of memory words from an integrated circuit memory of a contactless tag, comprising the sending by a remote interrogation unit to the contactless tag of a specific... |
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7974275 |
Saturated datagram aging mechanism
Methods for aging datagrams in the memory portion of a datagram distribution device or other network device are provided. According to some of these methods, an attribute of each datagram entering... |
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7962705 |
System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address... |
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7882295 |
Non-system bus width data transfer executable at a non-aligned system bus address
Disclosed are a method and apparatus of non-system bus width data transfer executable at a non-aligned system bus address. In one embodiment, a method of a controller is described. The method... |
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7853773 |
Program memory space expansion for particular processor instructions
A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion... |
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7849255 |
Pseudo-bidimensional randomly accessible memory using monodimensional sequentially-accessiblle memory structure
A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for... |
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7836273 |
Fast data access through page manipulation
A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data... |
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7818538 |
Hashing and serial decoding techniques
A serial decoding technique may employ one or more circular shift register strings in which an input to an element of a shift register string may be gated by either an address input or the inverse... |
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7788450 |
Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the... |
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7765380 |
Fast data access through page manipulation
A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data... |
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7739251 |
Incremental maintenance of an XML index on binary XML data
Techniques are provided for incrementally maintaining an XML index built to access XML data that is encoded in binary XML form. Rather than delete and reinsert index entries of all the nodes of a... |
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7707385 |
Methods and apparatus for address translation from an external device to a memory of a processor
Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to... |
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7694083 |
System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address... |
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7668983 |
System for designing data structures
Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d... |
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7664939 |
Method and apparatus for detecting false operation of computer
A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is... |
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7664929 |
Data processing apparatus with parallel operating functional units
A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each... |
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7640391 |
Integrated circuit random access memory capable of automatic internal refresh of memory array
A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending... |
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7636834 |
Method and apparatus for resetting a gray code counter
Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write... |
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7636817 |
Methods and apparatus for allowing simultaneous memory accesses in a programmable chip system
Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure.... |
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7631164 |
Modulo arithmetic
A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31)... |
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7596569 |
Method and program for space-efficient representation of objects in a garbage-collected system
A system includes a processor for executing a collector program to perform a method (e.g., a method of collection). The method includes using an object model during a collection phase that is... |
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RE40904 |
Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer
The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute... |
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7579683 |
Memory interface optimized for stacked configurations
A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so... |