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9003099 Disc device provided with primary and secondary caches  
In a disc device according to the present invention, when a controller 2 abandons a block from a cache memory 4 used as a primary cache, it is determined whether or not the number of readings of...
8977818 Combined transparent/non-transparent cache  
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a...
8954674 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8938585 Transparent processing core and L2 cache connection  
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling...
8909871 Data processing system and method for reducing cache pollution by write stream memory access patterns  
A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having...
8788581 Method and device for performing caching of dynamically generated objects in a data communication network  
A method for maintaining a cache of dynamically generated objects. The method includes storing in the cache dynamically generated objects previously served from an originating server to a client....
8700864 Self-disabling working set cache  
A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working...
8688911 Transparent processing core and L2 cache connection  
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling...
8578097 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
8516149 System for operating NFSv2 and NFSv3 clients with federated namespace  
An information retrieval system having: a client adapted for accessing a plurality of file sets stored on one of a plurality of file servers; a plurality of file servers configured to operate with...
8504777 Data processor for processing decorated instructions with cache bypass  
A method includes determining if a data processing instruction is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a...
RE44128 Adaptive resource controlled write-back aging for a data storage device  
A method for determining an aging period for retaining a write-back data in a cache memory prior to writing the write-back data to a storage media is determined through use of a write-back aging...
8386718 Method and apparatus for managing application data in a shared cache of a mobile electronic device  
According to embodiments described in the specification, a method and apparatus for managing memory in a mobile electronic device are provided. The method comprises: receiving a request to install...
8261257 Method and apparatus for transferring firmware between an operating system and a device in a host  
A host system includes an operating system having a user space and a kernel space with a memory. A device driver performs download cycles to download a firmware file from the user space to the...
8244981 Combined transparent/non-transparent cache  
In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a...
8219758 Block-based non-transparent cache  
In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of...
8108617 Method to bypass cache levels in a cache coherent system  
Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass...
8103721 Computing system and method of changing I/O configuration thereof  
A computing system includes: first and second I/O interfaces that are associated with a server; and an I/O management unit that connects the server with the first and second I/O interfaces. The...
8074026 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems  
A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory...
7921184 System and method for performing flash crowd caching of dynamically generated objects in a data communication network  
The present invention is directed towards a “flash crowd” technique for handling situations where the cache receives additional requests, e.g.,. nearly simultaneous requests, for the same object...
7870191 Computing system and method of changing I/O configuration thereof  
A computing system includes: first and second I/O interfaces that are associated with a server; and an I/O management unit that connects the server with the first and second I/O interfaces. The...
7849269 System and method for performing entity tag and cache control of a dynamically generated object not identified as cacheable in a network  
The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the...
7849270 System and method for performing entity tag and cache control of a dynamically generated object not identified as cacheable in a network  
The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the...
7836261 Managing caching of data on a client  
Embodiments include retrieving data of a web page from a remote system in response to a request for the web page. It is determined that the web page is indicated in a data structure that indicates...
7734842 Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages  
A computer-implemented method, apparatus, and computer program product are disclosed for managing direct memory access (DMA) write page faults using a pool of substitute pages. A computer system...
7711896 Storage system that is connected to external storage  
A first storage system is connected to a second storage system, and an external device within the first storage system is provided to a host as a device of the second storage system. The second...
7698506 Partial tag offloading for storage server victim cache  
A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes...
7356650 Cache apparatus and method for accesses lacking locality  
Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a...
7254673 Provision of a victim cache within a storage cache hierarchy  
Apparatus, methods, and program products for storing data address a first cache and a second cache. The second cache is capable of operating in a first mode wherein data read for storage in the...
7237065 Configurable cache system depending on instruction type  
A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic...
7185149 Selective storage in a cache memory device  
A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when...
7167964 Memory defragmentation in chipcards  
The basic idea comprised of the present invention is to provide two sets of descriptors having each at least three descriptors and each set is used in an alternating manner for defining the...
7117315 Method and apparatus for creating a load module and a computer product thereof  
Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which...
7080169 Receiving data from interleaved multiple concurrent transactions in a FIFO memory having programmable buffer zones  
A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent...
7076612 Cache interface circuit for automatic control of cache bypass modes and associated power savings  
A cache interface circuit includes a processor interface for receiving memory access requests from a processor, and for transmitting memory data back to the processor in response to processor...
7055006 System and method for blocking cache use during debugging  
A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also...
7017009 Cache memory device  
A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when...
6981112 Dynamic cache disable  
An apparatus, program product and method utilize a cache payback parameter for selectively and dynamically disabling caching for potentially cacheable operations performed in connection with a...
6865650 System and method for hierarchical data storage  
A system and method for storing data, the system having one or more storage devices, caches data from a sender into a first random-access structure located in a first cache level, caches data from...
6681297 Software controlled cache configuration based on average miss rate  
A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a level three (L3) physical memory....
6587928 Scheme for segregating cacheable and non-cacheable by port designation  
Requests are identified as being for a cacheable object or a non-cacheable object according to information included in a Uniform Resource Locator (URL) associated with the object. For example, the...
6415360 Minimizing self-modifying code checks for uncacheable memory types  
A processor employs an SMC check apparatus. The SMC check apparatus may minimize the number of explicit SMC checks performed for non-cacheable stores. Cacheable stores may be handled using any...
6415362 Method and system for write-through stores of varying sizes  
A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are...
6397382 Dynamic software code instrumentation with cache disabling feature  
A method and system of monitoring code as it is executed by a target processor is provided for debugging, etc. Standardized software code function preamble and postamble instructions are...
6389527 Microprocessor allowing simultaneous instruction execution and DMA transfer  
The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an...
6360300 System and method for storing compressed and uncompressed data on a hard disk drive  
A system and method for organizing compressed data and uncompressed data in a storage system. The method and system include a compressor for compressing a data block into a compressed data block,...
6345320 DMA address buffer and cache-memory control system  
A system includes a main-memory unit, an input/output-control unit which performs a write operation with respect to the main-memory unit by way of direct memory access, and a central-control unit...
6343345 Cache blocking of specific data to secondary cache with a first and a second OR circuit  
A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines...
6338119 Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance  
A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or “I/O” page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with...
6304944 Mechanism for storing system level attributes in a translation lookaside buffer  
A method and apparatus for improving the efficiency of the cacheability (and other attribute) determination by making the information from the region register available during linear to physical...

Matches 1 - 50 out of 85 1 2 >