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9032153 Use of flash cache to improve tiered migration performance  
For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of...
9026747 Memory device with a logical-to-physical bank mapping cache  
A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and...
9026695 Asymmetrical processing multi-core system and network device  
An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of...
9021213 System and method for sharing media in a computer network  
A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device...
9021181 Memory management for unifying memory cell conditions by using maximum time intervals  
A method includes accepting data for storage in a memory that is partitioned into multiple memory regions. A memory region is selected for storing the data. At least part of the data is stored in...
9015415 Multi-processor computing system having fast processor response to cache agent request capacity limit warning  
An apparatus is described that includes a plurality of processors, a plurality of cache slices and respective cache agents. Each of the cache agents have a buffer to store requests from the...
9015416 Efficient cache validation and content retrieval in a content delivery network  
Some embodiments provide systems and methods for validating cached content based on changes in the content instead of an expiration interval. One method involves caching content and a first...
9013991 Multicore processor including two or more collision domain networks  
Implementations and techniques for multicore processors having a domain interconnection network configured to associate a first collision domain network with a second collision domain network in...
9015525 Smart active-active high availability DAS systems  
A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active...
9009409 Cache region concept  
A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a...
9003129 Techniques for inter-storage-processor cache communication using tokens  
A method, performed at a first storage processor (SP) connected to a mirroring second SP, includes (a) receiving a write command at the first SP from a host directed to a particular address of a...
9003121 Multi-ported memory with multiple access support  
A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of...
8996789 Handling high priority requests in a sequential access storage device having a non-volatile storage cache  
Modified tracks for write requests to a sequential access storage medium in a sequential access storage device are cached in a non-volatile storage, which is a faster access device than the...
8996810 System and method of detecting cache inconsistencies  
A system and method of detecting cache inconsistencies among distributed data centers is described. Key-based sampling captures a complete history of a key for comparing cache values across data...
8990511 Multiprocessor, cache synchronization control method and program therefor  
There is provided a cache synchronization control method by which contents of a plurality of caches can be synchronized without a programmer explicitly setting a synchronization point, and the...
8977878 Reducing current leakage in L1 program memory  
An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling a sleep mode in the L1 program...
8965995 Wireless storage management system  
A wireless storage management system adapted for being used in an electronic product for wirelessly communicating with a plurality of wireless storage devices includes an identity module assigning...
8966178 Populating a first stride of tracks from a first cache to write to a second stride in a second cache  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
8959279 Populating a first stride of tracks from a first cache to write to a second stride in a second cache  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
8959287 Managing caches for reporting storage system information  
A method is used in managing caches for reporting storage system information. A cache is created. The cache includes information associated with a set of storage objects of a data storage system....
8959289 Data cache block deallocate requests  
A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is...
8949535 Cache updating  
Technology is described for performing cache data invalidations. The method may include identifying cache update information at a first cache. The cache update information may identify a cache...
8949536 Prefetching source tracks for destaging updated tracks in a copy relationship  
A point-in-time copy relationship associates tracks in a source storage with tracks in a target storage. The target storage stores the tracks in the source storage as of a point-in-time. A...
8949533 Method and node entity for enhancing content delivery network  
The present invention prdvides a method and a caching node entity for ensuring at least a predetermined number of a content object to be kept stored in a network, comprising a plurality of cache...
8949540 Lateral castout (LCO) of victim cache line in data-invalid state  
A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect...
8949534 Multi-CPU system and computing system having the same  
A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to...
8949546 Network cache system for reducing redundant data  
Embodiments include a local cache management system that is configured to be coupled to a local cache and that includes an index engine configured to store fingerprints of message segments stored...
8943272 Variable cache line size management  
According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line...
8935477 Managing caching of extents of tracks in a first cache, second cache and storage  
Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible...
8935476 Managing caching of extents of tracks in a first cache, second cache and storage  
Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible...
8930629 Data cache block deallocate requests in a multi-level cache hierarchy  
In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a...
8930636 Relaxed coherency between different caches  
One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more...
8930626 Cache management system and method  
A method and computer program product for dividing a cache memory system into a plurality of cache memory portions. Data to be written to a specific address within an electromechanical storage...
8924663 Storage system, computer-readable medium, and data management method having a duplicate storage elimination function  
The storage system includes a first auxiliary storage device, a second auxiliary storage device, and a main storage device, and also includes a data management unit which stores and keeps, in the...
8924653 Transactional cache memory system  
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an...
8918580 Storage device with buffer memory including non-volatile RAM and volatile RAM  
A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer...
8909866 Prefetching to a cache based on buffer fullness  
A processor transfers prefetch requests from their targeted cache to another cache in a memory hierarchy based on a fullness of a miss address buffer (MAB) or based on confidence levels of the...
8909865 Method and apparatus for plug and play, networkable ISO 18000-7 connectivity  
A device may comprise a Universal Serial Bus (USB) interface and a wireless interface operable to communicate in accordance with the ISO 18000-7 standard. The device may be operable to receive a...
8909872 Computer system with coherent interconnection  
A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is...
8904033 Buffering media content  
Media content is downloaded on a media device. Portions of the media content are buffered successively during the download in a buffer on the device. During the buffering, the buffered portions...
8904117 Non-shared write-back caches in a cluster environment  
Various systems and methods for performing write-back caching in a cluster. For example, one method can involve a first node detecting that no failover nodes are available. A determination is made...
8898374 Flash memory device and method for managing flash memory device  
A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a...
8898393 Optimized ring protocols and techniques  
Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a...
8886880 Write cache management method and apparatus  
A method for destaging data from a memory of a storage controller to a striped volume is provided. The method includes determining if a stripe should be destaged from a write cache of the storage...
8886885 Systems and methods for operating a plurality of flash modules in a flash memory file system  
Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash...
8874680 Interconnect delivery process  
A method for enforcing data integrity in an RDMA data storage system includes flushing data write requests to a data storage device before sending an acknowledgment that the data write requests...
8874845 Cache storage optimization in a cache network  
In one embodiment, a method includes receiving data at a cache node in a network of cache nodes, the cache node located on a data path between a source of the data and a network device requesting...
8874852 Data cache block deallocate requests in a multi-level cache hierarchy  
In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a...
8868834 Efficient cache validation and content retrieval in a content delivery network  
Some embodiments provide systems and methods for validating cached content based on changes in the content instead of an expiration interval. One method involves caching content and a first...
8862825 Processor supporting coarse-grained array and VLIW modes  
A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be...