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8966168 Memory and method for storing integrated serial data as divided data in parallel memories, performing read control based on a number of valid memories, and controlling integration of the divided data  
An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided...
8954687 Memory hub and access method having a sequencer and internal row caching  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory...
8874837 Embedded memory and dedicated processor structure within an integrated circuit  
An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random...
8832393 Alignment for multiple FIFO pointers  
In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO...
RE45097 High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory  
An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output...
8774305 Bit slip circuitry for serial data signals  
Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register...
8631195 Content addressable memory having selectively interconnected shift register circuits  
A search system for detecting whether one or more overlapping sequences of input characters match a regular expression including a prefix string preceding an intermediate expression having a...
8589641 Combined parallel/serial status register read  
Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One...
8477383 Processing based on command and register  
An image processing apparatus that applies image processing to image data read from a memory, the image processing apparatus including: an image processing input circuit that acquires a command...
8477897 Bit slip circuitry for serial data signals  
Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register...
8341362 System, method and apparatus for memory with embedded associative section for computations  
A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and...
8327091 Combined parallel/serial status register read  
Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One...
8316178 Buffering of data transfers for direct access block devices  
Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the...
8225034 Hybrid instruction buffer  
In one embodiment, a storage buffer includes a plurality of storage locations configured to store a plurality of incoming instructions. The storage buffer also includes a shift FIFO that is...
8166218 Memory buffers for merging local data from memory modules  
An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a parallel-in-serial-out (PISO) shift...
8156314 Incremental state updates  
A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The...
8122189 Methods for logically combining range representation values in a content addressable memory  
A method may include comparing a first content addressable memory (“CAM”) entry with a first key value to generate a first comparison result; comparing each of multiple second CAM entries with a...
8122190 Method and system for reconfigurable memory-based permutation implementation  
Memory-based permutation methods and systems are provided for the permutation of data. The memory-based permutation methods and systems provide flexibility and reconfigurability while reducing...
8098655 Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath  
A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue...
8060721 Apparatus and method for a synchronous multi-port memory  
A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate...
8037282 Register having security function and computer system including the same  
A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a...
8000469 Authentication engine architecture and method  
Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data...
7996604 Class queue for network data switch to identify data memory locations by arrival time  
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming...
7979607 Cascadable high-performance instant-fall-through synchronous first-in-first-out (FIFO) buffer  
An apparatus and method of operating a cascadable, instant-fall-through First In, First Out (FIFO) buffer is provided. The method comprises receiving a first data element at an input of a FIFO...
7941595 Methods and systems for a memory section  
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
7937640 Video over IP network transmission system  
Methods are disclosed for maintaining a quality video stream in Internet Protocol (IP) mode include dynamically adjusting IP packet-loss periods and loss distances between IP packet-loss events.
7930472 Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor  
A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data...
7890673 System and method for accessing non processor-addressable memory  
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs,...
7865255 Audio buffering system and method of buffering audio in a multimedia receiver  
An audio buffering system in a multimedia receiver includes an audio interface coupled to an incoming audio signal for generating a digital audio signal having transmitted therein a plurality of...
7849258 Storage apparatus and data verification method for the same  
A controller unit for the storage apparatus executes the following: giving each data block, which is a data constituent unit, an identification number indicating that the relevant data has been...
7844837 Electronic device and timer therefor with tamper event time stamp features and related methods  
An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may...
7814266 Partial row expansion by logically combining range representation values in content addressable memory  
A method and apparatus to reduce the number of rule entries used to implement ranging matching in a Content Addressable Memory (“CAM”) array. A first CAM entry is stored in a single CAM cell of an...
7809901 Combined parallel/serial status register read  
Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One...
7783827 Data processor having a memory controller with cache memory  
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
7773453 FIFO peek access  
Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the...
7769753 Method and system for retrieving a data pattern  
A data retrieval system includes a retrieval request block for generating a retrieval key including a current state number and a current character string including N characters latched from an...
7747020 Technique for implementing a security algorithm  
Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is...
7743237 Register file bit and method for fast context switch  
A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to...
7673095 FIFO memory architecture and method for the management of the same  
A FIFO memory with a frequency f and a size of M n-bit words, to successively store n-bit words received serially at an input and give said words serially at an output in the order in which they...
7672335 Non-integer word size translation through rotation of different buffer alignment channels  
A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each...
7657706 High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory  
An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output...
7606969 Programmable logic devices  
An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register...
7583663 Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath  
A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue...
7568066 Reset system for buffer and method thereof  
A reset system for a buffer and a method thereof are disclosed. The reset system of the present invention includes a resettable flag in the buffer and a control unit. The reset method is to set...
7548472 Logic embedded memory having registers commonly used by macros  
A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has...
7523353 Method for detecting hang or dead lock conditions  
A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user...
7512311 Data output apparatus and method with managed buffer  
A data output apparatus includes a disk drive for driving a magneto-optical disk. Compressed image data recorded on the magneto-optical disk is transferred from the magneto-optical disk to an...
7509451 Method and circuit for updating a software register in semiconductor memory device  
A method and circuit for updating a software register is disclosed, wherein the software register is updated using data received through a data I/O pad, and the updated data is read and...
7484061 Method for performing swap operation and apparatus for implementing the same  
A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a...
7467274 Method to increase the life span of limited cycle read/write media  
A file system technique extends the life cycle of limited read/write media. Rewrite cycles of each file and/or each region of the media may be tracked. Different regions of the media are...

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