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9043520 Interrupt control method and multicore processor system  
In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an...
9043521 Technique for communicating interrupts in a computer system  
A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an...
9026704 Priority based connection arbitration in a SAS topology to facilitate quality of service (QoS) in SAS transport  
A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in...
9015397 Method and apparatus for DMA transfer with synchronization optimization  
A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of...
9009377 Edge-triggered interrupt conversion in a system employing level-sensitive interrupts  
In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate...
8959270 Interrupt distribution scheme  
In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor...
8959382 Controlling communication of a clock signal to a peripheral  
A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the...
8943252 Latency sensitive software interrupt and thread scheduling  
Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated...
8938737 Delivering interrupts directly to a virtual processor  
Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt...
8898361 Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment  
Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to...
8892802 Enhancing interrupt handling in a virtual environment  
Systems and methods for enhancing the handling of interrupts in a virtual computing environment are disclosed. A CPU is configured such that the CPU, when in a virtual machine (VM) mode, directs...
8866826 Method and apparatus for dispatching graphics operations to multiple processing resources  
Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes...
8862786 Program execution with improved power efficiency  
Program execution with improved power efficiency including a computer program that for performing a method that includes determining a current power state of a processor. Low power state...
8843684 Performing call stack sampling by setting affinity of target thread to a current process to prevent target thread migration  
A sample is generated based on an event. Further, an interrupt handler captures information for an interrupted thread on a current processor. In addition, an affinity of the interrupted thread is...
8811417 Cross-channel network operation offloading for collective operations  
A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be...
8812761 System and method for adjusting power usage to reduce interrupt latency  
A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a...
8806232 Systems and method for hardware dynamic cache power management via bridge and power manager  
In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The...
8799547 Data packet processing method for a multi core processor  
A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network interface for forming a connection...
8799694 Adaptive recovery for parallel reactive power throttling  
Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for...
8799696 Adaptive recovery for parallel reactive power throttling  
Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for...
8756357 Data processor and control system  
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to...
8725922 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Data processor and control system
 
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to...
8725921 Virtual multi-processor system  
A virtual multi-processor system includes a plurality of logic processors. Moreover, the virtual multi-processor system includes a logic processor controller configured to allocate a time slice to...
8706941 Interrupt virtualization  
In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an...
8688882 Systems on chips having interrupt proxy functions and interrupt processing methods thereof  
Provided is a system on chip (SoC) capable of rapidly processing interrupts generated in various modules without causing an error. The SoC includes a processor configured to process a task, a...
8645602 Microcomputer  
Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in...
8612660 Interrupt latency measurement  
A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator...
8595541 Data processing modules requiring different average clock frequencies having a common clock and a clock gating circuit for deleting clock pulses applied to the modules at times consistent with data sourcing and sinking capabilities  
A method and apparatus are provided for docking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means...
8589612 Computer system including an interrupt controller  
A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode...
8578080 Secure handling of interrupted events utilizing a virtual interrupt definition table  
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still...
8560749 Techniques for managing power consumption state of a processor involving use of latency tolerance report value  
Techniques are described for determining a temporary latency tolerance report (tLTR) value. A processing unit has to respond to a device interrupt within a duration specified by tLTR to ensure no...
8560750 Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment  
Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to...
8549200 Multiprocessor system configured as system LSI  
A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor...
8510492 System and method for communication handshaking between a master processors and a slave processor  
System and method for handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor are described. In one...
8510489 Computing device and serial communication method of the computing device  
A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an...
8499112 Storage control apparatus  
An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first...
8489788 Data processor and control system  
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to...
8489789 Interrupt virtualization  
In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an...
8484648 Hardware multi-threading co-scheduling for parallel processing systems  
A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware...
8478924 Interrupt coalescing for outstanding input/output completions  
In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O)...
8463971 Approach for distributing interrupts from high-interrupt load devices  
A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the...
8438442 Method and apparatus for testing a data processing system  
A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the...
8407387 Multi-thread processor and the multi-thread processor's interrupt processing method having interrupt processing that is processed by an associated hardware thread  
A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow,...
8392643 Data processing device, semiconductor integrated circuit device, and abnormality detection method  
A data processing device for detecting the abnormal operation of a CPU is provided. The data processing device comprises a CPU, an interrupt counter, and a counter-abnormal-value detection...
8386684 Data processing system and method of interrupt handling  
A data processing system is provided which comprises at least two processing units (100, 101, 102) each for executing a plurality of tasks and an interrupt handling unit (200) for receiving an...
8341438 Information processing device for assigning interrupts to a first CPU or a second CPU based on a sleeping state  
An information processing device of the present invention comprises a main CPU capable of taking at least two states which are an operating state and a sleeping state, a sub-CPU having power...
8321614 Dynamic scheduling interrupt controller for multiprocessors  
Technologies are generally described herein for handling interrupts within a multiprocessor computing system. A priority level associated with a current task for each processor of the...
8316439 Anti-virus and firewall system  
An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic....
8312195 Managing interrupts using a preferred binding between a device generating interrupts and a CPU  
A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The...
8312198 Technique for communicating interrupts in a computer system  
A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an...

Matches 1 - 50 out of 262 1 2 3 4 5 6 >