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9026705 |
Interrupt processing unit for preventing interrupt loss
Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that... |
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9003094 |
Optimistic interrupt affinity for devices
A computing apparatus determines that a virtual processor of a guest has been moved from a first physical processor of a host to a second physical processor of the host. The computing apparatus... |
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8971537 |
Access control protocol for embedded devices
The client requests from the authentication and authorization server a capability for accessing the target server. The authentication and authorization server sends client a capability (capC,S)... |
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8966149 |
Emulation of an input/output advanced programmable interrupt controller
Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt... |
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8938737 |
Delivering interrupts directly to a virtual processor
Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt... |
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8924615 |
Communication of message signalled interrupts
A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing... |
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8914566 |
Managing interrupts
A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware... |
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8909836 |
Interrupt controller, apparatus including interrupt controller, and corresponding methods for processing interrupt request event(s) in system including processor(s)
An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a... |
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8909835 |
Computer system and method of controlling computer system
CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not... |
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8898361 |
Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment
Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to... |
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8880764 |
Pessimistic interrupt affinity for devices
A computing apparatus identifies that a first physical processor of a host has forwarded information regarding a device interrupt for a device to a second physical processor executing at least one... |
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8856416 |
Method and apparatus for processing latency sensitive electronic data with interrupt moderation
Numerous embodiments of a method and apparatus for processing latency sensitive electronic data with interrupt moderation are disclosed. |
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8838852 |
Programmable interrupt routing system
A method and apparatus to operate programmable routing logic comprise receiving, from a fixed function block, a first request, responsive to the first request, forwarding the first request to a... |
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8811417 |
Cross-channel network operation offloading for collective operations
A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be... |
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8719589 |
Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values
A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS... |
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8694688 |
Disk controller for implementing efficient disk I/O for a computer system
A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer... |
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8656079 |
Method and apparatus for remapping interrupt types
A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt... |
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8615619 |
Qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring... |
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8612992 |
Operating systems
A method of enabling multiple different operating systems to run concurrently on the same RISC computer, comprising selecting a first operating system to have a relatively high priority (the... |
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8578340 |
Recording and replaying computer program execution with recorded execution event breakpoints
A computer program execution record and replay system providing recorded execution event breakpoints is described. In one embodiment, for example, in the record and replay system, a method for... |
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8578080 |
Secure handling of interrupted events utilizing a virtual interrupt definition table
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still... |
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8572729 |
System, method and computer program product for interception of user mode code execution and redirection to kernel mode
A system, method and computer program product are provided. In use, code is executed in user mode. Further, the execution of the code is intercepted. In response to the interception, operations... |
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8566495 |
Systems, methods and apparatus for data communication
Implementations of systems, methods and apparatus include aspects of resource conservation strategies that may be useful for a USB compliant device that experiences resource limitations over... |
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8560750 |
Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment
Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to... |
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8549200 |
Multiprocessor system configured as system LSI
A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor... |
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8544022 |
Transactional memory preemption mechanism
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction... |
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8484389 |
AV renderer peripheral with dual inerrupt lines for staggered interrupts
An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two... |
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8478923 |
Interrupt suppression by processing just first interrupt of a same type
A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts... |
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8478924 |
Interrupt coalescing for outstanding input/output completions
In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O)... |
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8468284 |
Converting a message signaled interruption into an I/O adapter event notification to a guest operating system
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An... |
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8458387 |
Converting a message signaled interruption into an I/O adapter event notification to a guest operating system
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An... |
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8453143 |
Reducing the latency of virtual interrupt delivery in virtual machines
The latency of virtual interrupt delivery in virtual machines is reduced by normalizing and exposing the virtual interrupt routing information of each VM to a privileged domain such as the... |
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8438323 |
Communication processing apparatus, communication processing method, control method and communication device of communication processing apparatus
A communication processing apparatus (101) includes: a MAC unit (106) receiving a packet; a classification unit (107) classifying the received packet; a transfer control unit (104) transferring... |
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8424015 |
Transactional memory preemption mechanism
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction... |
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8386683 |
Information processing apparatus, interrupt control device and interrupt control method
An information processing device in which interrupts are generated when some events are occurred. The information processing device includes: an interrupt generating unit to generate an interrupt;... |
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8380906 |
Method and system for implementing interrupt service routines
Methods, computer-readable media, and systems for interrupt handling in Java™ are provided. In some illustrative embodiments, a method for interrupt handling in Java software that executes on a... |
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8380908 |
Emulation of an input/output advanced programmable interrupt controller
Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt... |
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8380724 |
Grouping mechanism for multiple processor core execution
A concurrent grouping operation for execution on a multiple core processor is provided. The grouping operation is provided with a sequence or set of elements. In one phase, each worker receives a... |
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8369365 |
Network terminal and computer readable medium
A network terminal includes an operating system on which a plurality of user environments can run in parallel, a plurality of calling units corresponding to the plurality of user environments... |
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8316439 |
Anti-virus and firewall system
An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic.... |
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8285904 |
Flexible notification mechanism for user-level interrupts
A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from... |
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8261284 |
Fast context switching using virtual cpus
Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in... |
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8255604 |
Interrupt vector piggybacking
A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to... |
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8255603 |
User-level interrupt mechanism for multi-core architectures
A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an... |
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8234430 |
Apparatus and method with controlled switch method
An embedded microcontroller system comprises a central processing unit, a system controller for receiving and handling an interrupt, a register having storage locations containing sets of... |
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8201170 |
Operating systems are executed on common program and interrupt service routine of low priority OS is modified to response to interrupts from common program only
A method of enabling multiple different operating systems to run concurrently on the same computer, comprising selecting a first operating system to have a relatively high priority (the realtime... |
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8151028 |
Information processing apparatus and control method thereof
An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having... |
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8145819 |
Method and system for stealing interrupt vectors
A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system... |
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8135884 |
Programmable interrupt routing system
A method and apparatus for a programmable interrupt routing system is described. |
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8131901 |
Interrupt control for virtual processing apparatus
A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware 26 and virtual interface hardware 28. Hypervisor software... |