Matches 1 - 50 out of 87 1 2 >


Match Document Document Title
8930602 Providing adaptive bandwidth allocation for a fixed priority arbiter  
In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one...
8843681 Techniques for accessing memory, system and bus arbitration  
Method, system, bus arbitration device for accessing a memory are described. According to one embodiment, priorities of N function modules accessing the memory are compared to obtain location...
8694705 Information processing device  
To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of...
8631272 Duplicate-aware disk arrays  
A duplicate-aware disk array (DADA) leaves duplicated content on the disk array largely unmodified, instead of removing duplicated content, and then uses these duplicates to improve system...
8613046 Far-end control method with security mechanism  
The present invention relates to a far-end control method with a security mechanism including a host transmitting an identification code through the PSTN (Public switched telephone network) to the...
8140921 System for elevator electronic safety device  
An elevator electronic safety system in which reliability of malfunction check can be improved by performing a malfunction check on memory data, an address bus, and a data bus. A check on the...
8069283 Method of processing and prioritizing at least one logical data stream for transmission over at least one physical data stream  
Method of processing data of at lease one data stream, data processing module for processing at a of at least one data stream, data processing system comprising such module, computer program...
7913024 Differentiating traffic types in a multi-root PCI express environment  
Mechanisms for differentiating traffic types in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual...
7908416 Data processing unit and bus arbitration unit  
An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating...
7660928 Abitration circuit providing stable operation regardless of timing for read and write requests  
The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in...
7328291 System and method for controlling the service engagement in a data bus system  
Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores...
7315909 Hierarchized arbitration method  
An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of...
7266626 Method and apparatus for connecting an additional processor to a bus with symmetric arbitration  
A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An...
7203779 Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus  
A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to...
7152173 Method and control apparatus for controlling startup of multiple IDE—HDDs  
The present invention provides a method and a control apparatus (1) for sequentially controlling the spinning up of a number of IDE_HDDs (30) included in one computer or network server. The method...
7072996 System and method of transferring data between a processing engine and a plurality of bus types using an arbiter  
A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a...
7051132 Bus system and path decision method therefor  
A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an...
6976108 System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities  
A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus...
6901487 Device for processing data by means of a plurality of processors  
A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per...
6898766 Simplifying integrated circuits with a common communications bus  
When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage. However, custom designs are more expensive...
6889276 Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus  
A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions....
6745273 Automatic deadlock prevention via arbitration switching  
A method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B)...
6721833 Arbitration of control chipsets in bus transaction  
A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second...
6587868 Computer system having peer-to-peer bus bridges and shadow configuration registers  
A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write...
6502149 Plural bus data storage system  
A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a plurality of memory regions and...
6397281 Bus arbitration system  
A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a memory and a plurality of...
6339807 Multiprocessor system and the bus arbitrating method of the same  
An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the...
6304933 Method and apparatus for transmitting data on a bus  
A method for transmitting data on a bus having multiple data lines is disclosed. Each of the data lines within the bus is assigned a unique binary value. During data transmissions, only one of the...
6286070 Shared memory access device and method  
A bus controller for a CCD digital still camera arbitrates competing requests by multiple microcontrollers for a shared memory. One of the microcontrollers is designated to have a higher priority...
6223244 Method for assuring device access to a bus having a fixed priority arbitration scheme  
Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a "fair share" of...
6202117 Host adapter integrated circuit having autoaccess pause  
A host adapter integrated circuit has a dedicated circuit which detects an attempted access of a digital resource (for example, SCSI bus interface circuitry) from a system bus (for example, a PCI...
6052513 Multi-threaded bus master  
Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or...
5974497 Computer with cache-line buffers for storing prefetched data for a misaligned memory access  
In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses...
5950229 System for accelerating memory bandwidth  
A computer system and method process memory requests for access to a computer memory. The computer system arbitrates between current memory requests based on an immediately previous memory request...
5935230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs  
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
5930486 Method and device for gracious arbitration of access to a computer system resource  
A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a...
5923859 Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus  
Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of...
5905878 Method for controlling access to a computer bus  
A bus controller controls access to a computer bus by a plurality of bus requesters. The bus controller activates a priority bus request line on the computer bus regardless of which of plural...
5901297 Initialization mechanism for symmetric arbitration agents  
An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each...
5901296 Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus  
Data is transferred over a bus from one device to another, or between one device and another system resource, such as a central processor. This data is classified into one of several types. "Hard...
5794072 Timing method and apparatus for interleaving PIO and DMA data transfers  
The present invention is directed at prioritizing and interleaving data transfer protocols between storage mediums and main memories. The invention includes a controller interface that is...
5794013 System and method for testing computer components in development environments  
A device emulator for use in testing pre-release program code emulates and replaces a first storage device such as a SCSI CD ROM drive containing the program code on CD ROM with a second storage...
5784624 Multiple asynchronous event arbitrator  
An arbitrator for selectively permitting access to a common resource by a priority device and two non-priority devices, includes a priority request reception device for receiving a priority...
5706469 Data processing system controlling bus access to an arbitrary sized memory area  
A novel data processing system is disclosed. Least significant bits of an address of a to-be-accessed memory of a number corresponding to a minimum specified range of a plurality of...
5642488 Method and apparatus for a host computer to stage a plurality of terminal addresses  
An apparatus and method having a terminal address designation for each source, such as an end terminal. The terminal addresses have a predetermined priority assigned thereto for permitting...
5611058 System and method for transferring information between multiple buses  
A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred...
5583999 Bus arbiter and bus arbitrating method  
A plurality of priority determining units determine a bus use among a plurality of bus masters on the basis of bus request signals respectively from the bus masters and thereby generate bus grant...
5551010 Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU  
A memory accessing device is coupled to a first bus which connects a first buffer storage unit in a central processing unit to a second buffer storage unit. The memory accessing device can access,...
5546547 Memory bus arbiter for a computer system having a dsp co-processor  
An arbitration scheme for a computer system in which a digital signal processor resides on the computer system's memory bus without requiring a block of dedicated static random access memory. An...
5541670 Electric apparatus and connector  
A connector that has three input/output ports and that can connect any two of the ports is used with a cable box that selects a channel from a CATV signal for a VCR and a TV, which also have...

Matches 1 - 50 out of 87 1 2 >