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8797062 
Configurable IC's with large carry chains
Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each... 

8745120 
Adder
According to an embodiment, an adder includes first and second wave computing units and a threshold wave computing unit. Each of the first and second wave computing units includes a pair of first... 

8516030 
Carry lookahead circuit and carry lookahead method
A carry lookahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first... 

8248102 
Configurable IC'S with large carry chains
Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each... 

8244791 
Fast carry lookahead circuits
A fast lookahead carry adder includes adder logic and lookahead carrypath logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit... 

8086657 
Adder structure with midcycle latch for power reduction
A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage... 

7933940 
Cyclic segmented prefix circuits for mesh networks
Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh... 

7899860 
Method and system for highspeed floatingpoint operations and related computer program product
A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit... 

7836113 
Dedicated logic cells employing configurable logic and dedicated logic functions
A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or lookup table (LL), a dedicated logic... 

7743085 
Configurable IC with large carry chains
Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each... 

7680874 
Adder
An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the... 

7613763 
Apparatus and method for converting, and adder circuit
An apparatus and method for converting a dualrail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output... 

7516173 
Carryskip adder having merged carryskip cells with sum cells
A multibit adder includes a carry chain, a carryskip network, sum cells, and a carrysum cell. The carry chain propagates, generates, or kills carryin bits. The carryskip network is coupled to... 

7440991 
Digital circuit
Disclosed is a digital circuit which comprises input signals A[n−1:0], SH[log2n−1:0], and DAT[n−1:0], a barrel shifter for outputting data B[n−1:0] obtained by shifting the signal DAT by the bits... 

7406495 
Adder structure with midcycle latch for power reduction
A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage... 

7395307 
Carry lookahead circuit and adder using same
A carry lookahead circuit for an adder to decrease circuit size and power consumption. The carry lookahead circuit is composed of 2input NAND gates 101, 102, 2input NOR gate 103, ANDNOR type... 

7313586 
Addersubtracter circuit
An addersubtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input... 

7299355 
Fast SHA1 implementation
Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multiloop and/or multiround authentication algorithms may be performed on... 

7290027 
Circuit suitable for use in a carry lookahead adder
An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate,... 

7219118 
SIMD addition circuit
A system for adding multiple sets of numbers via a fixedwidth adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a... 

7206802 
Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic
A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection... 

7205791 
Bypassable carry chain in a programmable logic device
A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set... 

7191205 
Function block
A function block allows a multiplier and a multiinput multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth... 

7185043 
Adder including generate and propagate bits corresponding to multiple columns
An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions... 

7152089 
Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks
A circuit that performs a prefix computation. This circuit includes an Nbit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . .... 

7028069 
Dynamic circuit using exclusive states
The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion... 

6988121 
Efficient implementation of multiprecision arithmetic
The present invention provides an efficient implementation of multiprecision arithmetic, such as for a microprocessor. For example, an implementation of multiprecision arithmetic is provided that... 

6954773 
Providing an adder with a conversion circuit in a slack propagation path
In one embodiment of the present invention, a highspeed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance.... 

6937062 
Specialized programmable logic region with lowpower mode
In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a lowpower mode so that they do not switch. For... 

6918024 
Address generating circuit and selection judging circuit
An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address... 

6877069 
Historybased carry predictor for data cache address generation
An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum... 

6868489 
Carry generation in address calculation
Embodiments are provided in which the generation of a carry of a sum of two numbers can be implemented by adding only some most significant bits of the two numbers and assuming that the sum of the... 

6839729 
Method and apparatus for a multipurpose domino adder
A method and apparatus for a multipurpose adder is described. The method includes calculation of an initial sum for each corresponding Nbit portion of a received addend signal and a received... 

6832235 
Multiple block adder using carry increment adder
A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a... 

6782406 
Fast CMOS adder with nullcarry lookahead
A nullcarrylookahead adder is configured to generate and propagate a nullcarry signal within and through blocks and groups of blocks within the adder. The nullcarry signal terminates the... 

6769007 
Adder circuit with a regular structure
One embodiment of the present invention provides an apparatus for facilitating an addition operation between two Nbit numbers, wherein the apparatus has a regular structure. The apparatus... 

6742014 
Conditional carry encoding for carry select adder
The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and... 

6674921 
Method of image sampling and apparatus thereof
A method of image sampling and an apparatus thereof. The apparatus comprises: an adder; a first register, the output of which is fed back to the adder; a first multiplexer, which outputs a ratio... 

6647405 
Adder circuit, integrating circuit which uses the adder circuit, and synchronism detection circuit which uses the integrating circuit
An adding circuit which receives addend data and augend data, each of which consists of a plurality of bits, and sums the addend and augend data, comprises: a plurality of addition blocks, each of... 

6631393 
Method and apparatus for speculative addition using a limited carry
One embodiment of the present invention, an eight bit binary adder with a typical latency independent of its width, is described. The adder comprises a four bit adder for calculating bits S3S0 of... 

6598066 
Fast carryout generation
A carryout bit generator determines if a bit pattern from two positive numbers matches one of the patterns for which a carryout bit would be generated in addition. These patterns include a TnG... 

6584485 
4 to 2 adder
A fourinput to twooutput adder is disclosed. The fourinput/twooutput adder includes a sumlookahead full adder and a modified full adder. The sumlookahead full adder includes an XOR3 block... 

6584484 
Incorporation of splitadder logic within a carryskip adder without additional propagation delay
An nbit carryskip adder includes a number of carryskip stages and a logic circuit associated with one or more of the stages. The logic circuit includes splitadder logic and carryskip logic... 

6571269 
Noisetolerant digital adder circuit and method
A digital adder circuit is implemented using a KoggeStone architecture. Various embodiments utilize singleended domino circuits, to which are input singleended primary addends. Dualfunction... 

6567836 
Multilevel carryskip adder
Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carryskip paths. In one implementation, such a binary adder includes a network of... 

6560625 
Fast digital adder
A carry lookahead digital adder that adds a first operand A of n bits and a second operand B of n bits, with n=2m, including: a first block calculating couples of signals Pq and Gq from the bits... 

6546411 
Highspeed radix 100 parallel adder
The present invention provides an improved method and apparatus for performing decimal arithmetic using conventional parallel binary adders. In a first aspect of the present invention, a method... 

6539413 
Prefix tree adder with efficient sum generation
An nbit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. The computation stages for each of the bit... 

6529931 
Prefix tree adder with efficient carry generation
An nbit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of... 

6519622 
Designing addition circuits
A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of... 