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Document Title 

8326909 
Arithmetic or logical operation tree computation
A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements. The method comprises: a)... 

8140826 
Executing a gather operation on a parallel computer
Methods, apparatus, and computer program products are disclosed for executing a gather operation on a parallel computer according to embodiments of the present invention. Embodiments include... 

7978972 
Optical line terminal and optical network terminal
The optical line terminal has a PON transceiver including an error correction code decoder. The error correction decoder includes: a shortening compensation parameter table; and a syndrome... 

7941474 
Arithmetic circuit, arithmetic method, and information processing device
To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a... 

7882387 
Reconfigurable device and control method thereof
A reconfigurable device having a plurality of component elements each configured in accordance with configuration information, the device being adapted to determine whether an error in... 

7035891 
Reducedhardware soft error detection
A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction,... 

6330701 
Method relating to processors, and processors adapted to function in accordance with the method
The present invention relates to a method of utilizing information made available in a bit error check of data words belonging to instructions read into a processor having a first (11) and a... 

6038652 
Exception reporting on function generation in an SIMD processor
The present invention is a method and apparatus for reporting exception in a single instruction multiple data (SIMD) processor in computing an arithmetic function for a plurality of argument data.... 

5506800 
Selfchecking complementary adder unit
A selfchecking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple... 

5504917 
Method and apparatus for providing picture generation and control features in a graphical data flow environment
A method and apparatus for providing picture generation and control features using a graphical data flow environment. The present invention includes a plurality of virtual instruments or VIs that... 

5490072 
Method and system for detecting the proper functioning of an ABS control unit utilizing dual programmed microprocessors
A method and apparatus for detecting the proper functioning of an ABS control unit which utilizes dual programmed microprocessors, the second of which calculates mismatched wheel speed and both of... 

5430852 
Control transfer method in system with multiple arithmetic units each with independent microprogram control by transferring start address and branch condition codes
A microprogram control system has first and second microprogram control units and first and second arithmetic circuits corresponding to the first and second microprogram control units,... 

5428768 
System for checking comparison check function of information processing apparatus
A check system for checking a comparison check function of an information processing apparatus which includes first and second microprocessors includes a check part for supplying mutually... 

5323403 
Method and apparatus for maximizing process throughput
Two identical CRC circuits are cross coupled to make alternate CRC calculations based on the other CRC circuit's calculation. Throughput of the CRC code calculation is improved by applying... 

5018093 
High performance selfchecking adder having small circuit area
A carry select adder may be used in which carry inputs to ripple adder stages are not fixed. The adder stage determines which of the two ripple adders of that stage has output the correct sum... 

4641275 
Vector processor having pair process mode and single process mode
A vector processor has a main storage, a main memory control circuit, vector registers, data transfer circuits; an address register group, and vector arithmetic units. The vector processor... 

4326291 
Error detection system
In a throughput error detection system, a redundant logic unit is provided along with a required logic unit for simultaneous operation therewith. The required logic unit and redundant logic unit... 

4251873 
Digital computing apparatus particularly for controlling a gas turbine engine
A digital computing apparatus, particularly for use in controlling a gas turbine engine, comprises two identical computing devices each of which is responsive to identical time control signals and... 

4031374 
Error correction system for random access memory
An error correction system is provided for a random access memory system of the magnetic core or plated wire type, and which serves to render the memory system immune to the effects of nuclear... 

3986015 
Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection
A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of... 

3829668 
DOUBLE UNIT CONTROL DEVICE
In a double unit control device comprising a pair of information input units, a pair of arithmetical processing units and a pair of output units, each of the arithmetical processing units... 

3805039 
HIGH RELIABILITY SYSTEM EMPLOYING SUBELEMENT REDUNDANCY
A highly reliable system redundancy concept is disclosed wherein the system is divided into a number of substantially identical subelements wherein spare ones of the subelements may be substituted... 

3758760 
ERROR DETECTION FOR ARITHMETIC AND LOGICAL UNIT MODULES
A modular error detector for an adder of the type which provides both arithmetic and logical functions and incorporates carrylookahead addition is described. The error detector includes parity... 

3660646 
CHECKING BY PSEUDODUPLICATION
An error detection system is described which detects errors by performing a given arithmetic or logical operation using one data path followed by the performing of the same arithmetic or logic... 

3636331 
METHOD AND SYSTEM FOR THE AUTOMATIC CONTROL OF CHEMICAL PLANTS WITH PARALLELCONNECTED COMPUTER BACKUP SYSTEM
A method and system for the automatic control and regulation of chemical processes in chemical plants using digital process computers which comprises operating at least two identical computers in... 

3588484 
ERROR DETECTING SYSTEM OF ADDER


3405258 
Reliability test for computer check circuits


3078039 
Error checking system for a parallel adder


3058656 
Asynchronous addsubtract system
916,795. Digital calculating; checking. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 10, 1960 [Feb. 24, 1959], No. 4721/60. Class 106 (1). An adder performs addition, or subtraction by... 

3051387 
Asynchronous addersubtractor system
916,795. Digital calculating; checking. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 10, 1960 [Feb. 24, 1959], No. 4721/60. Class 106 (1). An adder performs addition, or subtraction by... 

3033453 
Computers
910,211. Digital electric calculating. MINNEAPOLISHONEYWELL REGULATOR CO. Nov. 28, 1958 [Dec. 2, 1957], No. 38553/58. Class 106 (1). Two computers are used in the accurate '' realtime "... 

3032265 
Error free data input system


3023958 
Information handling apparatus


2666578 
Switching control system


2340809 
Electrical calculating equipment
527,836. Calculatingapparatus. STANDARD TELEPHONES & CABLES, Ltd. (Hatton, W., and Kozma, L.). April 4, 1939, No. 10524. [Class 106 (i)] [Also in Group XXXIX] In a system in which a number of... 