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Document Title 

9009208 
Floatingpoint adder
Floating point adder circuitry 16, 18, 20 is provided with farpath circuitry 18 and nearpath circuitry 20. The farpath circuitry utilises a count of trailing zeros TZ and a difference in the... 

8965945 
Apparatus and method for performing floating point addition
An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each... 

8937989 
Channel estimation using linear phase estimation
Systems and methods are provided for channel estimation using linear phase estimation. These systems and methods enable improved channel estimation by estimating a linear channel phase between... 

8903881 
Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit
An arithmetic circuit for quantizing prequantized data includes a first input register to store firstformat prequantized data that includes a mantissa and an exponent, a second input register... 

8898214 
Method and apparatus to perform floating point operations
A method of subtracting floatingpoint numbers includes determining whether a first sign associated with a first floatingpoint number is unequal to a second sign associated with a second... 

8825727 
Softwarehardware adder
A data processing system, method and computer program product to receive generalpurpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The... 

8788561 
Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit
An arithmetic circuit calculates a correction value for a value that is obtained by an addsubtract operation of two values and that is expressed in a predetermined fixed precision. 

8745111 
Methods and apparatuses for converting floating point representations
A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic... 

8713085 
Systems and methods for a signed magnitude adder in one's complement logic
Disclosed herein are systems and methods for a signedmagnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's... 

8645449 
Combined floating point adder and subtractor
Circuitry (fixed or configured in a programmable device) for performing floating point addition and subtraction uses approximately the same resources as required for either operation separately.... 

8630371 
Channel estimation using linear phase estimation
Systems and methods are provided for channel estimation using linear phase estimation. These systems and methods enable improved channel estimation by estimating a linear channel phase between... 

8620983 
Leading sign digit predictor for floating point near subtractor
An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position.... 

8615540 
Arithmetic logic unit for use within a flight control system
An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive... 

8615542 
Multifunction floating point arithmetic pipeline
A scalable engine having multiple datapaths, each of which is a unique multifunction floating point pipeline capable of performing a four component dot product on data in a single pass through... 

8601047 
Decimal floatingpoint adder with leading zero anticipation
A decimal floatingpoint (DFP) adder includes a decimal leadingzero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a... 

8554819 
System to implement floating point adder using mantissa, rounding, and normalization
A computation processor outputs whether a carryout is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes... 

8549054 
Arithmetic processing apparatus and arithmetic processing method
In an arithmetic processing apparatus, a dividing unit divides a second bit string into a loworder bit part having a bit width equal to a first bit width and a highorder bit part which is higher... 

8489665 
Communication apparatus, method of checking received data size, multiple determining circuit, and multiple determination method
A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2α to a variable V. If a positive number determining section determines that... 

8489663 
Decimal floatingpoint adder with leading zero anticipation
A decimal floatingpoint (DFP) adder includes a decimal leadingzero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a... 

8484267 
Weight normalization in hardware without a division operator
Weight normalization in hardware or software without a division operator is described, using only right bit shift, addition and subtraction operations. A right bit shift is performed on an... 

8463835 
Circuit for and method of providing a floatingpoint adder
A floatingpoint adder circuit is described. The circuit comprises an input multiplexer coupled to receive a first input value and a second input value; an addersubtractor circuit selectively... 

8423600 
Accumulating operator and accumulating method for floating point operation
An accumulating operator is applicable to a digital data processor to realize an output floating point number in response to a first floating point number and a second floating point number. The... 

8402075 
Mechanism for fast detection of overshift in a floating point unit of a processing device
A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The... 

8380769 
Filter operation unit and motioncompensating device
A filter operation unit that performs a multiplyaccumulate operation on input data and a filter coefficient group including a plurality of coefficients using Booth's algorithm. The filter... 

8332453 
Shifter with allone and allzero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result
A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input... 

8250126 
Efficient leading zero anticipator
Embodiments of the present invention provide a system that estimates the location of the leading zero or the leading one in the result of an addition of floatingpoint numbers A and B. The system... 

8239438 
Method and apparatus for implementing a multiple operand vector floating point summation to scalar function
Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a... 

8219604 
System and method for providing a double adder for decimal floating point operations
A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The... 

8214416 
Floatingpoint addition acceleration
Embodiments of the present invention generate a normalized floatingpoint sum from at least two floatingpoint addends. The mantissa of an unnormalized floatingpoint sum is generated. A pointer... 

8214417 
Subnormal number handling in floating point adder without detection of subnormal numbers before exponent subtraction
In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa... 

8185570 
Threeterm input floatingpoint addersubtractor
The addersubtractor includes a preprocessing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and... 

8170695 
Appliance incorporating load selectivity without employment of smart meters
Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal... 

8166085 
Reducing the latency of sumaddressed shifters
The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is... 

8161091 
Method for performing decimal floating point addition
A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a... 

8161090 
Floatingpoint fused addsubtract unit
In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floatingpoint fused addsubtract circuit. The method further includes simultaneously... 

8131795 
High speed adder design for a multiplyadd based floating point unit
A method is provided for improving a highspeed adder for FloatingPoint Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry... 

8069200 
Apparatus and method for implementing floating point additive and shift operations
A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at... 

8060549 
Method and apparatus for accumulating floating point values
A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is... 

8046400 
Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor
A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and... 

7991817 
Method and a circuit using an associative calculator for calculating a sequence of nonassociative operations
An apparatus and method that use an associative calculator for calculating a sequence of nonassociative operations on a set of input data, comprising: using the associative calculator to... 

7982496 
Busbased logic blocks with optional constant input
A busbased logic block for an integrated circuit includes a provision for placing an arbitrary constant onto a data bus in the logic block. An exemplary logic block has multibit first and second... 

7873688 
Processing method and computer system for summation of floating point data
A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends... 

7872497 
Flexible carry scheme for field programmable gate arrays
A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster... 

7814138 
Method and apparatus for decimal number addition using hardware for binary number operations
According to embodiments of the subject matter disclosed in this application, decimal floatingpoint additions and/or decimal fixedpoint additions may be implemented using existing hardware for... 

7746100 
Flexible adder circuits with fast carry chain circuitry
Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a... 

7720898 
Apparatus and method for adjusting exponents of floating point numbers
A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers,... 

7716264 
Method and apparatus for performing alignment shifting in a floatingpoint unit
An apparatus for performing alignment shifting in a floatingpoint unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second... 

7707236 
Methods and apparatus for an efficient floating point ALU
The present invention provides an improved technique for performing a near processing path exponent difference in an arithmetic logic unit (ALU) of a microprocessor. In one embodiment, an... 

7668892 
Data processing apparatus and method for normalizing a data value
A data processing apparatus and method are provided for normalizing a data value to produce a result value. The data processing apparatus includes prediction logic for generating a shift... 

7663400 
Flexible carry scheme for field programmable gate arrays
A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster... 