Match Document Document Title
9040425 Methods of forming printable integrated circuit devices and devices formed thereby  
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to...
9040421 Methods for fabricating integrated circuits with improved contact structures  
Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a...
9040424 Methods of forming single crystal silicon structures and semiconductor device structures including single crystal silicon structures  
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic...
9034755 Method of epitaxially forming contact structures for semiconductor transistors  
Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate...
9029265 Method for forming semiconductor structure  
A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate. The dielectric layer includes a curable...
9029271 Methods of patterning block copolymer layers  
A method of patterning a block copolymer layer includes: providing a guide pattern on a surface of a substrate, the guide pattern including sidewalls each elongated in a longitudinal direction and...
9012244 Method to form multiple trenches utilizing a grayscale mask  
The present disclosure relates to a method to form a plurality of openings within a substrate with a single photo exposure and a single etch process. A photoresist layer is disposed over a...
9012304 Semiconductor die singulation method  
In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of...
9005463 Methods of forming a substrate opening  
A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the...
8999846 Elongated via structures  
An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator...
8999862 Methods of fabricating nano-scale structures and nano-scale structures fabricated thereby  
Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on...
8993447 LED device with improved thermal performance  
An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device...
8994182 Dielectric solder barrier for semiconductor devices  
The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the...
8987141 Method of manufacturing Si-based high-mobility group III-V/Ge channel CMOS  
A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer...
8987133 Titanium oxynitride hard mask for lithographic patterning  
A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The...
8987140 Methods for etching through-silicon vias with tunable profile angles  
The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma...
8986921 Lithographic material stack including a metal-compound hard mask  
A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask...
8980748 Substrate polishing method, semiconductor device and fabrication method therefor  
A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate...
8981337 Membrane projection lithography  
The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An...
8980754 Method of removing a photoresist from a low-k dielectric film  
Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k...
8975717 Trench process and structure for backside contact solar cells with polysilicon doped regions  
A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped...
8975152 Methods of reducing substrate dislocation during gapfill processing  
Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and...
8975729 Integrating through substrate vias into middle-of-line layers of integrated circuits  
A semiconductor wafer has an integrated through substrate via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through...
8974678 Methods using block co-polymer self-assembly for sub-lithographic patterning  
Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers,...
8975186 Double patterning methods and structures  
Various embodiments provide double patterning methods and structures. In an exemplary method, a to-be-etched layer can be provided. A stress layer can be formed on the to-be-etched layer. The...
8975639 Substrate for epitaxial growth  
A surface of a substrate consists of a plurality of neighboring stripes. Longer edges of the flat surfaces are parallel one to another and planes of these surfaces are disoriented relatively to...
8969206 Triple patterning NAND flash memory with stepped mandrel  
A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to...
8962485 Reusing active area mask for trench transfer exposure  
A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer...
8963234 Semiconductor device  
The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate...
8956950 Method of manufacturing semiconductor devices  
A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a...
8951908 Method for manufacturing semiconductor device  
A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating...
8952485 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability  
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller...
8945404 Self-formed nanometer channel at wafer scale  
A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate. A nanowire is patterned on the film. Insulating material is deposited on the...
RE45361 Semiconductor device manufacturing method having high aspect ratio insulating film  
The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper...
8946076 Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells  
Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically...
8940641 Methods for fabricating integrated circuits with improved patterning schemes  
Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer...
8940597 In-situ metal gate recess process for self-aligned contact application  
A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes...
8940640 Source/drain structure of semiconductor device  
The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate...
8940639 Methods and structures for using diamond in the production of MEMS  
A MEMS device with movable MEMS structure and electrodes is produced by fabricating electrodes and shielding the electrodes with diamond buttons during subsequent fabrication steps, such as the...
8937007 Semiconductor device  
A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a...
8937017 Method and apparatus for etching  
Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a...
8932957 Method of fabricating a FinFET device  
A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask...
8932956 Far back end of the line stack encapsulation  
A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal...
8932904 Semiconductor device and method of manufacturing the same  
A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or...
8932947 Methods for forming a round bottom silicon trench recess for semiconductor applications  
Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a...
8932955 Triple patterning NAND flash memory with SOC  
A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to...
8927433 Conductive via hole and method for forming conductive via hole  
Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an...
8927427 Anticipatory implant for TSV  
A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench...
8927436 Thin film transistor and method of manufacturing trench, metal wire, and thin film transistor array panel  
The present invention relates to a method for forming a trench that can remove residual particles in a trench using a metal mask, a method for forming a metal wire, and a method for manufacturing...
8921954 Method of providing a semiconductor structure with forming a sacrificial structure  
A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes...