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9034717 Semiconductor-on-insulator structure and method of fabricating the same  
Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A...
8999864 Silicon wafer and method for heat-treating silicon wafer  
A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for...
8865572 Dislocation engineering using a scanned laser  
A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a...
8865571 Dislocation engineering using a scanned laser  
A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of...
8846500 Method of forming a gettering structure having reduced warpage and gettering a semiconductor wafer therewith  
At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.
8816419 Semiconductor device  
Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals;...
8735859 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first...
8551837 Methods of fabricating high-K metal gate devices  
Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are...
8546928 Micromechanical housing comprising at least two cavities having different internal pressure and/or different gas compositions and method for the production thereof  
The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component...
8546862 Memory cell, an array, and a method for manufacturing a memory cell  
A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating...
8399280 Method for protecting an integrated circuit chip against laser attacks  
A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active...
8382894 Process for the preparation of silicon wafer with reduced slip and warpage  
Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 μm from the surface of...
8329563 Semiconductor device including a gettering layer and manufacturing method therefor  
A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface...
8293613 Gettering structures and methods and their application  
An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first...
8263876 Conductive substrate structure with conductive channels formed by using a two-sided cut approach and a method for manufacturing the same  
A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral...
8207048 Method for producing ordered nanostructures  
Method for producing nanostructures comprising: a step of providing a substrate (100) having a buried barrier layer (2) and above said barrier layer (2) a crystalline film (5) provided with a...
8164096 Organic light emitting diode flat panel display device having uniform electrical characteristics and method of manufacturing the same  
A flat panel display device, more particularly, an Organic Light Emitting Diode (OLED) display device having uniform electrical characteristics and a method of fabricating the same include: a thin...
8143910 Semiconductor integrated circuit and method of testing the same  
Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that...
8138066 Dislocation engineering using a scanned laser  
A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor...
8133769 Methods for gettering in semiconductor substrate  
A method for forming gettering sites and gettering impurities in a substrate layer includes producing a first masking layer over the substrate layer and patterning the masking layer to define...
8093089 Methods of manufacturing image sensors including gettering regions  
Method of manufacturing image sensors having a plurality of gettering regions. In the method, a gate electrode may be formed on a semiconductor substrate. A source/drain region may be formed in...
7799660 Method for manufacturing SOI substrate  
The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an...
7737004 Multilayer gettering structure for semiconductor device and method  
In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.
7573083 Transistor type ferroelectric memory and method of manufacturing the same  
A transistor type ferroelectric memory including: a substrate; a gate electrode formed above the substrate; a ferroelectric layer formed above the substrate to cover the gate electrode; a source...
7569693 Naphthalene-based semiconductor materials and methods of preparing and use thereof  
Provided are mono- and diimide naphthalene compounds for use in the fabrication of various device structures. In some embodiments, the naphthalene core of these compounds are mono-, di-, or...
7498620 Integration of phosphorus emitter in an NPN device in a BiCMOS process  
According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium...
7422951 Method of fabricating self-aligned bipolar transistor  
The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by...
7297630 Methods of fabricating via hole and trench  
A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a...
7297992 Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process  
According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium...
7211482 Method of forming a memory cell having self-aligned contact regions  
A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the...
7169674 Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier  
A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over...
7169664 Method of reducing wafer contamination by removing under-metal layers at the wafer edge  
According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel...
7135351 Method for controlling of thermal donor formation in high resistivity CZ silicon  
The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer...
6958264 Scribe lane for gettering of contaminants on SOI wafers and gettering method  
A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated...
6897084 Control of oxygen precipitate formation in high resistivity CZ silicon  
The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer...
6838321 SEMICONDUCTOR SUBSTRATE WITH DEFECTS REDUCED OR REMOVED AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE CAPABLE OF BIDIRECTIONALLY RETAINING BREAKDOWN VOLTAGE AND METHOD OF MANUFACTURING THE SAME  
An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion...
6815282 Silicon on insulator field effect transistor having shared body contact  
Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a...
6797547 Bladed silicon-on-insulator semiconductor devices and method of making  
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post...
6784051 Method for fabricating semiconductor device  
The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The...
6777272 Method of manufacturing an active matrix display  
A driver circuit integration type (monolithic type) active matrix display device having high performance is formed by using thin film transistors (TFT). While a nickel element is added t an...
6703281 Differential laser thermal process with disposable spacers  
MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal...
6693015 Method for improved processing and etchback of a container capacitor  
A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random...
6670259 Inert atom implantation method for SOI gettering  
The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one...
6551866 Method of manufacturing a semiconductor memory device  
A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single...
6433380 Integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein  
Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a...
6344384 Method of production of semiconductor device  
A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar...
6339011 Method of forming semiconductive active area having a proximity gettering region therein and method of processing a monocrystalline silicon substrate to have a proximity gettering region  
In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive...
6309938 Deuterated bipolar transistor and method of manufacture thereof  
A bipolar transistor and a method of manufacturing the transistor. The transistor includes: (1) a substrate having a base region, an emitter region and a base-emitter junction between said base...
6165867 Method to reduce aspect ratio of DRAM peripheral contact  
The present invention provides a method for reducing aspect ratio of DRAM peripheral contact so as to achieving a good contact etching and metal deposition by utilizing conventional equipment....
6140172 Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs and integrated circuitry  
The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor...

Matches 1 - 50 out of 92 1 2 >