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9041009 Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device  
A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of...
9040380 Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a...
9034701 Semiconductor device with a low-k spacer and method of forming the same  
A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate...
9034706 FinFETs with regrown source/drain and methods for forming the same  
A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The...
9034700 Integrated circuit devices including finFETs and methods of forming the same  
Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a...
9029226 Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices  
The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The...
9029227 P-channel flash with enhanced band-to-band tunneling hot electron injection  
A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a...
9012999 Semiconductor device with an inclined source/drain and associated methods  
A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate...
9006059 CMOS transistor and method for fabricating the same  
The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming...
9006071 Thin channel MOSFET with silicide local interconnect  
A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a...
9006057 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack...
8999798 Methods for forming NMOS EPI layers  
NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor...
8999799 Maskless dual silicide contact formation  
Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of...
8987101 Method of forming strained source and drain regions in a P-type finFET structure  
A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography...
8980702 Method of making a transistor  
A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active...
8975144 Controlling the shape of source/drain regions in FinFETs  
An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation...
8975142 FinFET channel stress using tungsten contacts in raised epitaxial source and drain  
Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain,...
8969152 Field-effect transistor (FET) with source-drain contact over gate spacer  
A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the...
8969924 Transistor-based apparatuses, systems and methods  
Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and...
8969931 Semiconductor devices with screening coating to inhibit dopant deactivation  
A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and...
8962400 In-situ doping of arsenic for source and drain epitaxy  
A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is...
8962412 Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same  
A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain...
8962433 MOS transistor process  
A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is...
8962434 Field effect transistors with varying threshold voltages  
A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers,...
8963157 Thin film transistor, array substrate, and manufacturing method thereof  
A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and...
8951875 Semiconductor structure  
A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first...
8951871 Semiconductor device and manufacturing method thereof  
This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the...
8946060 Methods of manufacturing strained semiconductor devices with facets  
A method for fabricating a semiconductor device, the method includes forming a gate stack over a major surface of a substrate. The method further includes recessing the substrate to form source...
8946034 Strained semiconductor device and method of making the same  
In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from...
8946007 Inverted thin channel mosfet with self-aligned expanded source/drain  
After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a...
8946064 Transistor with buried silicon germanium for improved proximity control and optimized recess shape  
A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of...
8946033 Merged fin finFET with (100) sidewall surfaces and method of making same  
A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of...
8941156 Self-aligned dielectric isolation for FinFET devices  
Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric...
8936987 PMOS transistors and fabrication methods thereof  
A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method...
8936988 Methods for manufacturing a MOSFET using a stress liner of diamond-like carbon on the substrate  
A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer...
8937299 III-V finFETs on silicon substrate  
A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the...
8927376 Semiconductor device and method of forming epitaxial layer  
A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor...
8927422 Raised silicide contact  
A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon...
8927377 Methods for forming FinFETs with self-aligned source/drain  
A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped...
8927374 Semiconductor device and fabrication method thereof  
A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained...
8927375 Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level  
Embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate; epitaxially growing a silicon-carbon layer on top...
8928090 Self-aligned contact structure for replacement metal gate  
A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric...
8921190 Field effect transistor and method of manufacture  
A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure...
8921191 Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same  
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are...
8916437 Insulated gate field effect transistor having passivated schottky barriers to the channel  
A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate...
8916443 Semiconductor device with epitaxial source/drain facetting provided at the gate edge  
A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first...
8916440 Semiconductor structures and methods of manufacture  
Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect...
8912059 Middle of-line borderless contact structure and method of forming  
Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a...
8912056 Dual epitaxial integration for FinFETS  
A dual epitaxial integration process for FinFET devices. First and second pluralities of fins and gates are formed, with some of the fins and gates being for NFETs and some of the fins and gates...
8912567 Strained channel transistor and method of fabrication thereof  
The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS)...