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Match Document Document Title
9029227 P-channel flash with enhanced band-to-band tunneling hot electron injection  
A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a...
9006094 Stratified gate dielectric stack for gate dielectric leakage reduction  
A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a...
8994107 Semiconductor devices and methods of forming the semiconductor devices including a retrograde well  
Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain...
8987105 SiC semiconductor device and method of manufacturing the same  
A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve...
8963239 800 V superjunction device  
A superjunction device includes a substrate having first and second main surfaces and a first doping concentration of a first dopant. A first semiconductor layer having a second doping...
8853010 Semiconductor device and method of fabricating the same  
A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and...
8841183 Nonvolatile semiconductor memory device and method for manufacturing the same  
On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon...
8841187 Semiconductor device and method for fabricating semiconductor device  
Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a...
8822293 Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices  
A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a...
8822294 Method for improving write margins of SRAM cells  
The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a...
8790981 Low cost high voltage power FET and fabrication  
A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g.,...
8759916 Field effect transistor and a method of forming the transistor  
Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a...
8691653 Semiconductor structure with reduced surface field effect and manufacturing process thereof  
A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second...
8664067 CMOS devices with reduced short channel effects  
An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration...
8664715 Isolated transistor  
A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may...
8643100 Field effect transistor having multiple effective oxide thicknesses and corresponding multiple channel doping profiles  
A FET includes a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective...
8633075 Semiconductor device with high voltage transistor  
A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions;implanting first impurity ions of a first conductivity type to form...
8609510 Replacement metal gate diffusion break formation  
Embodiments of the invention provide approaches for replacement metal gate (RMG) diffusion break formation. Specifically, a diffusion break is created after source/drain (S/D) formation, thereby...
8574991 Asymmetric transistor devices formed by asymmetric spacers and tilted implantation  
An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further...
8476684 Field effect transistors having improved breakdown voltages and methods of forming the same  
Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and...
8421163 Power module  
A power module comprises: first and second terminals; first and second switching elements having a first electrode and a second electrode which is connected to the second terminal; first and...
8389369 Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same  
An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not...
8330232 Nonvolatile memory device and method of forming the same  
A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a...
8294217 Semiconductor device and method of manufacturing semiconductor device  
The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate...
8263466 Channel strain induced by strained metal in FET source or drain  
A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a...
8222657 Light emitting apparatus  
A light emitting apparatus may include a gate metal positioned between a p-type contact and an n-type contact, a gate oxide or other dielectric stack positioned below and attached to the gate...
8216903 SRAM cell with asymmetrical pass gate  
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first...
8211773 SRAM cell with asymmetrical pass gate  
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first...
8158482 Asymmetric transistor devices formed by asymmetric spacers and tilted implantation  
An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further...
8154077 Semiconductor device  
According to an embodiment, a semiconductor device includes a gate electrode formed on a semiconductor substrate via an insulating layer; a source region including an extension region, a drain...
8119507 Lateral double-diffused metal oxide semiconductor (LDMOS) transistors  
Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can...
8089124 Lateral DMOS device and method for fabricating the same  
An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep...
8067289 Semiconductor device and manufacturing method thereof  
A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a...
8058129 Lateral double diffused MOS device and method for manufacturing the same  
A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface...
8030166 Lateral pocket implant charge trapping devices  
A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of...
8013381 Semiconductor device  
A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the...
8012836 Semiconductor devices and methods for fabricating the same  
Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed...
7998849 Semiconductor device used as high-speed switching device and power device  
A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface...
7968400 Short channel LV, MV, and HV CMOS devices  
Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates...
7955919 Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes  
A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode...
7927987 Method of reducing channeling of ion implants using a sacrificial scattering layer  
Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer...
7923327 Method of fabricating non-volatile memory device with concavely depressed electron injection region  
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with...
7843020 High withstand voltage transistor and manufacturing method thereof, and semiconductor device adopting high withstand voltage transistor  
A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a...
7829957 Semiconductor device and manufacturing method thereof  
A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are...
7821062 Field effect transistor and method for producing a field effect transistor  
A field effect transistor is provided having a source region, a drain region formed in a first well region, and a channel region. The first well region is doped with doping atoms of a first...
7745305 Method of removing an oxide and method of filling a trench using the same  
A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the...
7736984 Method of forming a low resistance semiconductor contact and structure therefor  
In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.
7718498 Semiconductor device and method of producing same  
A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed...
7645650 Double gated transistor and method of fabrication  
A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is...
7645665 Semiconductor device having shallow b-doped region and its manufacture  
A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the...

Matches 1 - 50 out of 435 1 2 3 4 5 6 7 8 9 >