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9029225 Method for manufacturing N-type MOSFET  
The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain...
9029227 P-channel flash with enhanced band-to-band tunneling hot electron injection  
A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a...
9006843 Source/drain extension control for advanced transistors  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
8987080 Methods for manufacturing metal gates  
Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate;...
8952462 Method and apparatus of forming a gate  
The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric...
8921181 Flourine-stabilized interface  
Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed...
8912527 Multi-quantum well structure and light emitting diode having the same  
A multi-quantum well structure includes two first barrier layers, two well layers sandwiched between the two first barrier layers, and a doped second barrier layer sandwiched between the two well...
8889518 LDMOS transistor with asymmetric spacer as gate  
The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on...
8835294 Method for improving thermal stability of metal gate  
The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure...
8796802 Semiconductor photodetector and radiation detector system  
Semiconductor photodetectors are provided that may enable optimized usage of an active detector array. The semiconductor photodetectors may have a structure that can be produced and/or configured...
8728903 Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode  
A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a...
8722523 Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure  
When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a...
8686511 Source/drain extension control for advanced transistors  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
8679902 Stacked nanowire field effect transistor  
A method for fabricating a nanowire field effect transistor device includes depositing a first sacrificial layer on a substrate, depositing a first layer of a semiconductor material on the first...
8664067 CMOS devices with reduced short channel effects  
An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration...
8664715 Isolated transistor  
A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may...
8633083 Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant  
A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed...
8629027 Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions  
An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or...
8586438 Semiconductor device and manufacturing method thereof  
Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower...
8574991 Asymmetric transistor devices formed by asymmetric spacers and tilted implantation  
An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further...
8570455 Semiconductor device, semiconductor device manufacturing method, liquid crystal display device and electronic apparatus  
A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating...
8563384 Source/drain extension control for advanced transistors  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
8524562 Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device  
A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS)...
8525257 LDMOS transistor with asymmetric spacer as gate  
The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on...
8455322 Silicon germanium heterojunction bipolar transistor structure and method  
Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal...
8445342 Short channel semiconductor devices with reduced halo diffusion  
A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after...
8404551 Source/drain extension control for advanced transistors  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
8389369 Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same  
An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not...
8361872 High performance low power bulk FET device and method of manufacture  
A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses...
8357574 Method of fabricating epitaxial structures  
A method for fabricating an integrated device is disclosed. The disclosed method provides improved formation selectivity of epitaxial films over a pre-determined region designed for forming an epi...
8357579 Methods of forming integrated circuits  
A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich...
8329566 Method of manufacturing a high-performance semiconductor device  
The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate...
8309420 Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications  
A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top...
8298879 Methods of fabricating metal oxide or metal oxynitride TFTS using wet process for source-drain metal etch  
The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting...
8258035 Method to improve source/drain parasitics in vertical devices  
A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer...
8236641 Semiconductor device with extension structure and method for fabricating the same  
A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation...
8216903 SRAM cell with asymmetrical pass gate  
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first...
8211773 SRAM cell with asymmetrical pass gate  
A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first...
8193060 Method of manufacturing a semiconductor device  
Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a...
8158482 Asymmetric transistor devices formed by asymmetric spacers and tilted implantation  
An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further...
8101475 Field effect transistor and method for manufacturing the same  
A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate...
8012836 Semiconductor devices and methods for fabricating the same  
Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed...
8007727 Virtual semiconductor nanowire, and methods of using same  
A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and...
7988470 Methods of fabricating metal oxide or metal oxynitride TFTs using wet process for source-drain metal etch  
The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting...
7936006 Semiconductor device with backfilled isolation  
An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric...
7923327 Method of fabricating non-volatile memory device with concavely depressed electron injection region  
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with...
7915110 MOS transistor manufacturing  
A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
7843020 High withstand voltage transistor and manufacturing method thereof, and semiconductor device adopting high withstand voltage transistor  
A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a...
7838369 Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications  
An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt...
7821062 Field effect transistor and method for producing a field effect transistor  
A field effect transistor is provided having a source region, a drain region formed in a first well region, and a channel region. The first well region is doped with doping atoms of a first...

Matches 1 - 50 out of 246 1 2 3 4 5 >