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9024291 Resistive memory device and fabrication method thereof  
A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the...
9023719 High aspect ratio memory hole channel contact formation  
A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a...
9018046 Area-efficient distributed device structure for integrated voltage regulators  
An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler...
9012318 Etching polysilicon  
Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
9012270 Metal layer enabling directed self-assembly semiconductor layout designs  
Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed...
9006040 Systems and methods for fabricating semiconductor devices having larger die dimensions  
A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are...
9006857 Platform comprising an infrared sensor  
An IR sensor includes a suspended micro-platform having a support layer and a device layer disposed thereon. IR absorbers are disposed in or on the device layer. IR radiation received by the IR...
9006093 Non-volatile memory (NVM) and high voltage transistor integration  
A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select...
8999766 ESD/antenna diodes for through-silicon vias  
Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the...
8993430 Manufacturing method of semiconductor device and semiconductor device  
According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an...
8981422 Semiconductor device and method of manufacturing the same  
To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over...
8969923 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning  
Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines...
8945984 Bump-on-trace methods and structures in packaging  
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder...
8945998 Programmable semiconductor interposer for electronic package and method of forming  
Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user...
8932912 One-time programmable device  
According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a...
8933431 Dual-plane memory array  
A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an...
8928014 Stress relief for array-based electronic devices  
In accordance with certain embodiments, an electric device includes a flexible substrate having first and second conductive traces on a first surface thereof and separated by a gap therebetween,...
8921898 Device including an array of memory cells and well contact areas, and method for the formation thereof  
A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a...
8921850 Oxide thin film transistor, method for fabricating TFT, array substrate for display device and method for fabricating the same  
A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film...
8921166 Structure and method for placement, sizing and shaping of dummy structures  
A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy...
8912052 Semiconductor device and structure  
A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including...
8907463 Semiconductor device including stacked semiconductor chips  
A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of...
8901530 Nonvolatile memory device using a tunnel oxide as a passive current steering element  
Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and...
8901526 Variable resistive memory device  
A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate...
8901632 Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology  
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer...
8883625 Method for decomposing lines of an electronic circuit  
A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines...
8860174 Recessed antifuse structures and methods of making the same  
Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit...
8853815 Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains  
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated...
8835894 Resistive memory structure and method for fabricating the same  
The present invention discloses a resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises...
8834729 Method of making bondable printed wiring member  
A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member...
8822968 Nonvolatile memory device and method for manufacturing same  
According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes...
8809128 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning  
The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality...
8809829 Phase change memory having stabilized microstructure and manufacturing method  
A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory...
8796145 Method of manufacturing metal-base substrate and method of manufacturing circuit board  
A method of manufacturing a metal-base substrate having an insulative adhesive layer and a conductor layer on a metal-based material is provided. The method includes the steps of dispersing a...
8791507 Semiconductor device  
A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate...
8791508 High density gallium nitride devices using island topology  
A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The...
8785306 Manufacturing methods for accurately aligned and self-balanced superjunction devices  
A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming...
8778700 Hydrogen barrier for ferroelectric capacitors  
An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for...
8759163 Layout of a MOS array edge with density gradient smoothing  
A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered...
8729675 Semiconductor device having line-type trench to define active region and method of forming the same  
A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions...
8728875 Ballasted polycrystalline fuse  
A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to...
8703597 Method for fabrication of a semiconductor device and structure  
A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a...
8703546 Activation treatments in plating processes  
A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an...
8697499 System of dynamic and end-user configurable electrical interconnects  
A dynamic and end-user configurable controlled impedance interconnect line includes a plurality of conductive pixels, a plurality of thin-film transition material interconnects to electrically...
8698519 Scalable non-blocking switching network for programmable logic  
A L-level permutable switching network (L-PSN) having switches and multiple levels of conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
8698119 Nonvolatile memory device using a tunnel oxide as a current limiter element  
Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and...
8679901 Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same  
A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of...
8664044 Method of fabricating land grid array semiconductor package  
A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid...
8658474 Contact and via interconnects using metal around dielectric pillars  
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect...
8659140 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate  
A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second...