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9042168 System and method for improving error distribution in multi-level memory cells  
A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a...
9036432 Method for controlling data write operation of a mass storage device  
A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage...
9036431 Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device  
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe...
9030889 Buffering systems for accessing multiple layers of memory in integrated circuits  
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of...
9013926 Non-volatile semiconductor storage device capable of increasing operating speed  
According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a...
9001596 Nonvolatile memory apparatus including sharing driver capable of performing both of read and write operation  
A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in...
9001557 Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device  
Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method...
8995203 Non-volatile memory device, driving method of memory controller controlling the non-volatile memory device and memory system including the memory controller and the non-volatile memory device  
The present inventive concept provides a driving method of memory controller controlling nonvolatile memory device using variable resistive element. The memory controller may control a plurality...
8995184 Adaptive operation of multi level cell memory  
A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states...
8988951 Method and device for writing block data to an embedded DRAM free of address conflicts  
Embodiments of the present invention provide a method and a device for writing data. The method includes: receiving a data block that is to be written in an EDRAM; obtaining, according to a status...
8982646 Semiconductor memory device including data transfer bus and data transfer method of the device  
According to one embodiment, a semiconductor memory device includes a memory cell array, a data bus, a transfer controller, column blocks, and a column selector. The data bus is divided into...
8982647 Resistive random access memory equalization and sensing  
Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism...
8971146 Dual-port SRAM with bit line clamping  
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver...
8953394 Semiconductor device capable of operating in both a wide input/output mode and a high-bandwidth mode  
A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and...
8953397 Semiconductor device and method of operating the same  
The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase...
RE45307 Non-volatile semiconductor storage device  
A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer...
8913444 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements  
A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value...
8913450 Memory cell array with reserved sector for storing configuration information  
A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line...
8902678 Voltage regulator  
A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction...
8891288 8T SRAM cell with one word line  
An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be...
8867283 Semiconductor memory device, operating method thereof, and data storage apparatus including the same  
A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first...
8867253 Semiconductor device having multiport memory  
A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a...
8861289 Multiport memory with matching address control  
In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a...
8854901 Read self timing circuitry for self-timed memory  
A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference...
8848464 Semiconductor device and method of driving semiconductor device  
A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the...
8848460 Semiconductor device having plural data buses and plural buffer circuits connected to data buses  
A plurality of buffer circuits and data buses coupled to the buffer circuits are included in a device. Each of the data buses includes first and second portions. The first portions of the data...
8837205 Multi-port register file with multiplexed data  
A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first...
8830774 Semiconductor memory device  
In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines...
8817555 Semiconductor memory device  
A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit...
8811068 Integrated circuit devices and methods  
An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and...
8804434 Pulse-based memory read-out  
A pulse-based memory read-out device, including: a pulse generator at a first end of a bit line and a detector at a second end of the bit line. The pulse generator is configured to send an...
8804413 Multi-free layer MTJ and multi-terminal read circuit with concurrent and differential sensing  
A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the...
RE45051 Page buffer circuit of memory device and program method  
A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least...
8767486 Output driver circuit, output driver system and semiconductor memory device  
The output driver circuit includes a plurality of pull-up sub-drivers that pull up a voltage at the output terminal according to a pull-up signal based on the output data. The output driver...
8767482 Apparatuses, devices and methods for sensing a snapback event in a circuit  
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be...
8750055 Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device  
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe...
8750065 Thermal management apparatuses with temperature sensing resistive random access memory devices and methods thereof  
An apparatus includes one or more temperature sensing and memory devices each having one or more memristors. A controller device is coupled to the temperature sensing and memory devices A...
8750054 Data input/output circuit and semiconductor memory device  
A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and...
8743602 Nonvolatile memory device  
Embodiments of present invention relate to a nonvolatile memory device that includes a first page buffer controlling any one of a first even bit line and a first odd bit line; a second page buffer...
8743629 Preloading data into a flash storage device  
Programmer's data that is transferred from a programming device (160) to a storage device (100) is initially stored in a memory device (120) of the storage device (100) by using a durable...
8724420 SRAM write assist apparatus  
An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage...
8711599 Polarization-coupled ferroelectric unipolar junction memory and energy storage device  
A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first...
8705266 Semiconductor device and method for controlling the same  
According to one embodiment, a semiconductor memory device includes a plurality of first interconnects which extend in a first direction and are arranged in a second direction perpendicular to the...
8705293 Compact sense amplifier for non-volatile memory suitable for quick pass write  
A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the...
8699261 Variable resistance nonvolatile memory device and driving method thereof  
A highly-reliable variable resistance nonvolatile memory device capable of a stable operation and a driving method of the variable resistance nonvolatile memory device are provided. A variable...
8699269 Systems and methods for improving error distributions in multi-level cell memory systems  
A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed...
8670281 Circuit for memory cell recovery  
An apparatus and method for combating the effects of bias temperature instability (BTI) and other variability in a memory cell. Bit lines connecting to a memory cell contain two alternate paths...
8665662 Early read after write operation memory device, system and method  
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device...
8665658 Tracking cell and method for semiconductor memories  
A semiconductor memory includes a memory array having at least one bit line, a tracking bit line, and a global tracking circuit. The tracking bit line is configured to emulate a voltage transition...
8665636 Semiconductor storage device  
According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A...