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9042157 Programmable volatile/non-volatile memory cell  
The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a...
9042162 SRAM cells suitable for Fin field-effect transistor (FinFET) process  
A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass...
9036405 Memory sense amplifier with multiple modes of operation  
Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The...
9036404 Methods and apparatus for SRAM cell structure  
An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at...
9030893 Write driver for write assistance in memory device  
A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write...
9030863 Read/write assist for memories  
An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The...
9025356 Fly-over conductor segments in integrated circuits with successive load devices along a signal path  
The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal...
9025394 Memory devices and control methods thereof  
A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and...
9019751 Process tolerant circuits  
Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from...
9019752 Static random access memory (SRAM) global bitline circuits for reducing power glitches during memory read accesses, and related methods and systems  
Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce...
9019753 Two-port SRAM write tracking scheme  
A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit...
9013914 Semiconductor memory device and method for controlling semiconductor memory device  
A semiconductor memory device includes word lines, bit line pairs intersecting the word lines, and memory cells arranged where the word lines and the bit line pairs intersect. A word line driver...
9013949 Memory access control system and method  
The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request...
9013943 Static random access memory circuit with step regulator  
Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a...
9007815 Method and apparatus for switching power in a dual rail memory  
A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column...
9007857 SRAM global precharge, discharge, and sense  
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global...
9007858 SRAM global precharge, discharge, and sense  
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global...
9007817 Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods  
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access...
9007816 Memory circuit and memory device  
To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that...
9001569 Input trigger independent low leakage memory circuit  
Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the...
9000503 Semiconductor device  
A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be...
9001601 Memory device including repair circuit and repair method thereof  
A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array....
9001570 Pseudo retention till access mode enabled memory  
A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An...
9001571 6T static random access memory cell, array and memory thereof  
A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access...
9001546 3D structure for advanced SRAM design to avoid half-selected issue  
Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed...
9001568 Testing signal development on a bit line in an SRAM  
An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected....
8995176 Dual-port SRAM systems  
Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a...
8995210 Write and read collision avoidance in single port memory devices  
A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first...
8995177 Integrated circuits with asymmetric transistors  
Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data...
8995208 Static random access memory devices having read and write assist circuits therein that improve read and write reliability  
Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by...
8995175 Memory circuit with PMOS access transistors  
A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one...
8988153 Ring oscillator with NMOS or PMOS variation insensitivity  
A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without...
8988932 Time processing method and circuit for synchronous SRAM  
A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various...
8988920 Semiconductor memory device  
A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the...
8982607 Memory element and signal processing circuit  
In a memory element including a pair of inverters, a capacitor which holds data, and a switching element which controls accumulating and releasing of electric charge of the capacitor are provided....
8982609 Memory having read assist device and method of operating the same  
A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first...
8976573 Apparatus for SRAM cells  
A memory cell comprises a first word line in a first interconnect layer, a first VSS line, a first bit line, a power source line, a second bit line and a second VSS line formed a second...
8976614 Tracking scheme for memory  
A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell...
8975917 Programmable logic device  
A programmable logic device includes a plurality of arithmetic circuits; a configuration changing circuit for changing a logic state of each of the plurality of arithmetic circuits by rewriting...
8976575 SRAM performance monitor  
A semiconductor circuit can include an array of static random access memory (SRAM) cells. A first SRAM cell may provide a first current through an insulated gate field effect transistor (IGFET)...
8976574 Process corner sensor for bit-cells  
An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output...
8976576 Static random access memory structures  
A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is...
8971096 Wide range multiport bitcell  
A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the...
8971097 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter  
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by...
8971138 Method of screening static random access memory cells for positive bias temperature instability  
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel...
8971099 Method of measuring threshold voltage of MOS transistor in SRAM array  
Methods of measuring threshold voltages of MOS transistors in a SRAM array are provided. The SRAM array includes array-arranged cells having a first pass NMOS transistor, a second pass NMOS...
8971095 Memory architecture  
A write circuit in a memory array includes a global data line, a switching circuit, and a first local data line coupled with the switching circuit and with a first plurality of memory cells. The...
8971098 Latch-based array with enhanced read enable fault testing  
A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master...
8971136 Memory device correcting the effect of collision of high-energy particles  
A memory device automatically correcting the effect of collisions of high-energy particles, comprising at least one memory cell, and further comprising: retention means for retaining, for a...
8971084 Context protection for a column interleaved memory  
A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the...