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9041204 Bonding pad structure with dense via array  
A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is...
9041160 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer...
9035459 Structures for improving current carrying capability of interconnects and methods of fabricating the same  
Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying...
9030013 Interconnect structures comprising flexible buffer layers  
A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a...
9030017 Z-connection using electroless plating  
An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component...
9018664 Semiconductor device and production method therefor  
An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive...
9018760 Solder interconnect with non-wettable sidewall pillars and methods of manufacture  
A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface....
9011570 Articles containing copper nanoparticles and methods for production and use thereof  
Articles containing a matrix material and plurality of copper nanoparticles in the matrix material that have been at least partially fused together are described. The copper nanoparticles are less...
9013042 Interconnection structure for semiconductor package  
An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the...
9006905 Semiconductor device with through silicon via and alignment mark  
A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and...
9006898 Conductive lines and pads and method of manufacturing thereof  
A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first...
9000595 Method of manufacturing semiconductor device and semiconductor device  
To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a...
8993442 Interconnect structure and method for forming the same  
Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening...
8994178 Interconnect structure and method for forming the same  
A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer...
8987875 Balanced stress assembly for semiconductor devices  
An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the...
8987910 Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and IC-substrates  
The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding...
8987905 Semiconductor package and method for manufacturing the same  
A semiconductor package includes a semiconductor device and a substrate, the semiconductor device including a straight line portion on an outer periphery and the substrate supporting the...
8987911 Silver-to-silver bonded IC package having two ceramic substrates exposed on the outside of the package  
A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA)...
8981466 Multilayer dielectric structures for semiconductor nano-devices  
Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and...
8981560 Method and structure of sensors and MEMS devices using vertical mounting with interconnections  
A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one...
8981564 Metal PVD-free conducting structures  
Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can...
8981401 Package for optical semiconductor device, optical semiconductor device using the package, and methods for producing same  
The present invention is a package for optical semiconductor devices, and an optical semiconductor device using the package, which can prevent discoloration of a plating layer formed on a lead...
8975670 Semiconductor device and structure for heat removal  
A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer,...
8975734 Semiconductor package without chip carrier and fabrication method thereof  
A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to...
8970033 Extending metal traces in bump-on-trace structures  
A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a...
8970043 Bonded stacked wafers and methods of electroplating bonded stacked wafers  
A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface...
8963326 Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration  
A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the...
8962478 Method to use self-repair Cu barrier to solve barrier degradation due to Ru CMP  
A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD;...
8957521 Mounted structure  
A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the...
8952538 Semiconductor device and method for manufacturing the same  
A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings...
8952543 Via connection structures, semiconductor devices having the same, and methods of fabricating the structures and devices  
A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer....
8946903 Electrically conductive laminate structure containing graphene region  
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the...
8946899 Via in substrate with deposited layer  
An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough...
RE45361 Semiconductor device manufacturing method having high aspect ratio insulating film  
The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper...
8946074 Method of making interconnect structure  
A method of forming a semiconductor device, comprising: providing a Si-containing layer; forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including a...
8946900 X-line routing for dense multi-chip-package interconnects  
X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of...
8941239 Copper interconnect structure and method for forming the same  
A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier...
8932911 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects  
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact...
8927986 P-type metal oxide semiconductor  
The disclosure provides a p-type metal oxide semiconductor material. The p-type metal oxide semiconductor material has the following formula: In1−xGa1−yMx+yZnO4+m, wherein M is Ca, Mg, or Cu,...
8927416 Semiconductor device and method of manufacturing the same  
A first insulating film is formed on a semiconductor substrate, an interconnect groove is formed in the first insulating film, the inside of the interconnect groove is filled with a metal film,...
8928125 Interconnects having sealing structures to enable selective metal capping layers  
Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom....
8922019 Semiconductor device having a copper plug  
Disclosed is a semiconductor device wherein an insulation layer has a via opening with an aluminum layer in the via opening and in contact with the last wiring layer of the device. There is a...
8921996 Power module substrate, power module, and method for manufacturing power module substrate  
A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint...
8916466 Method for manufacturing dual damascene wiring in semiconductor device  
A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating...
8912559 Group III nitride semiconductor light-emitting device  
A Group III nitride semiconductor light-emitting device, includes a groove having a depth extending from the top surface of a p-type layer to an n-type layer is provided in a region overlapping...
8912657 Semiconductor device  
The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern...
8912658 Interconnect structure with enhanced reliability  
An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with...
8912546 Thin film transistor and display device  
The present invention provides a technique by which a component forming a display device, such as a wiring can be formed with good adhesion. In the invention, a component forming a thin film...
8907485 Copper ball bond features and structure  
An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated...
8901734 Semiconductor device and method of forming column interconnect structure to reduce wafer stress  
An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel...