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9034755 Method of epitaxially forming contact structures for semiconductor transistors  
Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate...
9006895 Interconnect structures containing nitrided metallic residues  
A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues...
8993435 Low-k Cu barriers in damascene interconnect structures  
In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor...
8962478 Method to use self-repair Cu barrier to solve barrier degradation due to Ru CMP  
A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD;...
8946835 Magnetic device with different planarization areas  
A planarization process may planarize a media disk that has data trenches between data features and larger servo trenches between servo features. A filler material layer is deposited on the media...
8922018 Semiconductor device and semiconductor device manufacturing method  
According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap...
8901724 Semiconductor package with embedded die and its methods of fabrication  
Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The...
8896121 Chip assembly system  
An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is...
8884432 Substrate and assembly thereof with dielectric removal for increased post height  
An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections...
8883642 Method of manufacturing semiconductor device and semiconductor manufacturing apparatus  
In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating...
8853862 Contact structures for semiconductor transistors  
Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a...
8803317 Structures for improving current carrying capability of interconnects and methods of fabricating the same  
Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying...
8785901 Semiconductor devices having metal oxide patterns  
Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed...
8749064 Semiconductor device with a line and method of fabrication thereof  
A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer...
8710661 Methods for selective reverse mask planarization and interconnect structures formed thereby  
Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a...
8710660 Hybrid interconnect scheme including aluminum metal line in low-k dielectric  
A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k...
8669608 Method for manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device  
According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through...
8669182 Metal cap with ultra-low κ dielectric material for circuit interconnect applications  
An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect...
8653663 Barrier layer for copper interconnect  
A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary...
8558350 Metal-oxide-metal capacitor structure  
A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger...
8545998 Electroless deposition of platinum on copper  
Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto...
8541882 Stacked IC device with recessed conductive layers adjacent to interlevel conductors  
An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of...
8536704 Semiconductor device and method for fabricating the same  
An interlayer insulating film containing oxygen and carbon is formed on a semiconductor substrate. A groove is formed in the interlayer insulating film. An auxiliary film containing predetermined...
8518818 Reverse damascene process  
The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal...
8513777 Method and apparatus for generating reticle data  
A method for generating reticle data for forming a reticle. The method includes recognizing a non-layout region free from main chips in a process pattern, dividing the non-layout region into a...
8482125 Conductive sidewall for microbumps  
Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased...
8476766 Semiconductor memory device and method for manufacturing the same  
According to one embodiment, a semiconductor memory device includes a multilayer body, a second electrode film provided on the multilayer body, a second insulating film provided on the second...
8432037 Semiconductor device with a line and method of fabrication thereof  
A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer...
8415251 Electric component and component and method for the production thereof  
A method for producing an electrical component (1) is proposed, in which a ceramic base body (5) that contains a through-hole contact (10) and at least one metallization surface (20C)...
8394656 Method of creating MEMS device cavities by a non-etching process  
MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One...
8390120 Semiconductor device and method of fabricating the same  
A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over...
8390123 ULSI micro-interconnect member having ruthenium electroplating layer on barrier layer  
A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes a barrier layer formed on the substrate and...
8373276 Printed wiring board and method for manufacturing the same  
Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a...
8373070 Metal structure of flexible multi-layer substrate and manufacturing method thereof  
Disclosed is a metal structure of a multi-layer substrate, comprising a first metal layer and a dielectric layer. The first metal layer has an embedded base and a main body positioned on the...
8368211 Solderable top metalization and passivation for source mounted package  
A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not...
8368227 Semiconductor element and package having semiconductor element  
The present disclosure relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one...
8354751 Interconnect structure for electromigration enhancement  
An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a...
8334597 Semiconductor device having via connecting between interconnects  
A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in...
8304300 Method of manufacturing display device including transistor  
An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an...
8258629 Curing low-k dielectrics for improving mechanical strength  
An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the...
8232647 Structure and process for metallization in high aspect ratio features  
A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material...
8216932 Method of manufacturing semiconductor devices having metal lines  
The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor...
8178950 Multilayered through a via  
A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium...
8138604 Metal cap with ultra-low k dielectric material for circuit interconnect applications  
An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect...
8119519 Semiconductor device manufacturing method  
A method for making a semiconductor device including at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers...
8105942 CMP-first damascene process scheme  
An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric...
8106513 Copper damascene and dual damascene interconnect wiring  
A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper...
8089153 Method for eliminating loading effect using a via plug  
Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced....
8058731 Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance  
By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration...
8053357 Prevention of post CMP defects in CU/FSG process  
A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present...