Match
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Document |
Document Title |
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9035417 |
Parasitic inductance reduction for multilayered board layout designs with semiconductor devices
A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop... |
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9024407 |
Monitoring testkey used in semiconductor fabrication
A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS... |
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9013002 |
Iridium interfacial stack (IRIS)
An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a... |
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8987883 |
Semiconductor package with multiple conductive clips
One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad,... |
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8981445 |
Analog floating-gate memory with N-channel and P-channel MOS transistors
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is... |
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8963281 |
Simultaneous isolation trench and handle wafer contact formation
Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer... |
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8957493 |
Semiconductor device
A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first... |
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8952750 |
Semiconductor power modules and devices
An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a... |
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8946859 |
Device for detecting an attack in an integrated circuit chip
An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a... |
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8928109 |
Semiconductor device
A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the... |
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8907429 |
Semiconductor device, semiconductor integrated circuit, SRAM, and method for producing Dt-MOS transistor
A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to... |
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8896085 |
Semiconductor light-emitting element manufacturing method, lamp, electronic equipment, and mechanical apparatus
A semiconductor light-emitting element manufacturing method including: a first step in which a first n-type semiconductor layer is laminated onto a substrate in a first organometallic chemical... |
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8890338 |
Method of identifying and/or programming an integrated circuit
A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level... |
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8884396 |
Semiconductor device and manufacturing method thereof
According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second... |
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8876312 |
Lighting device and apparatus with spectral converter within a casing
In one embodiment, a light-emitting device having a substrate, a casing, a plurality of light source dies, a plurality of spectral converters and a plurality of optical structures is disclosed.... |
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8872303 |
Chip pad resistant to antenna effect and method
A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in... |
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8853789 |
Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation... |
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8841754 |
Semiconductor devices with stress relief layers
A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via... |
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8836074 |
Semiconductor memory device
A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as... |
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8835895 |
Memory device and fabrication process thereof
A resistive-change memory element-containing memory device including: a first memory element that includes a first resistive-change layer and a first electrode connected to the first... |
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8803284 |
Thick on-chip high-performance wiring structures
Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first... |
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8736015 |
Integrated circuit structure and method of forming the same
An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a... |
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8729658 |
Integrated circuit devices having buried interconnect structures therein that increase interconnect density
Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is... |
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8729640 |
Method and structure for radiation hardening a semiconductor device
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation.... |
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8692266 |
Circuit substrate structure
A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is... |
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8671565 |
Blind via capture pad structure fabrication method
A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture... |
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8669659 |
Semiconductor device and a method of manufacturing the same
A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of... |
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8664050 |
Structure and method to improve ETSOI MOSFETS with back gate
A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor... |
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8664754 |
High power semiconductor package with multiple conductive clips
One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad,... |
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8659113 |
Embedded semiconductor die package and method of making the same using metal frame carrier
An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe... |
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8648643 |
Semiconductor power modules and devices
An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a... |
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8642986 |
Integrated circuit having microelectromechanical system device and method of fabricating the same
An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a... |
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8581361 |
Semiconductor apparatus
A power supply wiring and a pad are arranged on a first wiring layer. Then, the power supply wiring and the pad are arranged so as not to be mutually overlapped. Signal wirings are arranged on a... |
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8552559 |
Very thick metal interconnection scheme in IC chips
A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective... |
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8536677 |
Capacitor structure
One or more embodiments relate to a capacitor structure comprising a first and second capacitor electrode. The first electrode may include a conductive strip having at least one wider portion and... |
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8530997 |
Double seal ring
A double seal ring for an integrated circuit includes a first seal ring with a first opening. The first seal ring surrounds the integrated circuit. A second seal ring with a second opening... |
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8507358 |
Composite wafer semiconductor
A composite wafer semiconductor device includes a first wafer and a second wafer. The first wafer has a first side and a second side, and the second side is substantially opposite the first side.... |
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8503212 |
Semiconductor memory apparatus with power-meshed structure
A semiconductor memory apparatus includes a plurality of banks each having a plurality of cell mats; a plurality of power lines disposed over predetermined portions of each of the plurality of... |
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8502338 |
Through-substrate via waveguides
A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A... |
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8497573 |
High power semiconductor package with conductive clip on multiple transistors
In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the... |
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8492868 |
Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer
A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the... |
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8487400 |
High performance system-on-chip using post passivation process
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a... |
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8487397 |
Method for forming self-aligned contact
An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor... |
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8476614 |
Memory device and fabrication process thereof
A memory device that includes a resistive-change memory element, the memory device includes: a first memory element that includes a first resistive-change layer and a first electrode connected to... |
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8470705 |
Chip pad resistant to antenna effect and method
A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in... |
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8471324 |
Semiconductor device
A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a... |
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8470635 |
Keyhole-free sloped heater for phase change memory
Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device. |
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8466535 |
Galvanic isolation fuse and method of forming the fuse
The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a... |
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8432015 |
Semiconductor device and wire bonding method
A semiconductor device (2) includes: a FLR (65) that is disposed on a semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding... |
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8405185 |
Semiconductor device and semiconductor module including the same
Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is... |