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9041007 Semiconductor device  
A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n−-drift layer. An interlayer insulating film covers the gate...
9041003 Semiconductor devices having a recessed electrode structure  
An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be...
9040383 Devices with gate-to-gate isolation structures and methods of manufacture  
Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate....
9035394 Semiconductor device  
A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the...
9035391 Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials  
A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect...
9035390 Thin film transistor substrate and method for producing same  
A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed...
9034709 Method for manufacturing semiconductor device  
A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD...
9035389 Layout schemes for cascade MOS transistors  
A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to...
9029235 Trench isolation MOS P-N junction diode device and method for manufacturing the same  
A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of...
9029959 Composite high-k gate dielectric stack for reducing gate leakage  
A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be...
9029951 Semiconductor device having well regions with opposite conductivity  
A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region...
9029841 Carbon nanotube devices with unzipped low-resistance contacts  
A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The...
9029954 Semiconductor device and manufacturing method therefor  
A semiconductor device according to the present invention has an n-type MIS transistor. The n-type MIS transistor has a first active region surrounded by a device isolation region in a...
9024392 Multi-port SRAM manufacturing  
Some embodiments relate to an integrated circuit including fin field effect transistors (FinFETs) thereon. The integrated circuit includes first and second active fin regions having a first...
9024355 Embedded planar source/drain stressors for a finFET including a plurality of fins  
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed...
9024364 Fin-FET with mechanical stress of the fin perpendicular to the substrate direction  
A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side...
9024387 FinFET with body contact  
A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single...
9018707 Semiconductor device  
A semiconductor device includes a first transistor group including first transistors, wherein each of the first transistors includes a first gate, and a first source and a first drain disposed...
9018708 Semiconductor device and method for fabricating the same  
A semiconductor device includes a substrate including a cell region and a peripheral circuit region, buried gates formed in the substrate of the cell region, a bit line formed over the cell region...
9012998 Gate depletion drain extended MOS transistor  
A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and...
9013003 Semiconductor structure and process thereof  
A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the...
9012277 In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices  
Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and...
9013001 Stress-generating shallow trench isolation structure having dual composition  
A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the...
9012999 Semiconductor device with an inclined source/drain and associated methods  
A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate...
9006835 Transistor with embedded Si/Ge material having reduced offset and superior uniformity  
A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first...
9006803 Semiconductor device and method for manufacturing thereof  
An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body,...
9006729 Semiconductor device and manufacturing method thereof  
It is an object to provide a method for manufacturing a highly reliable semiconductor device having a thin film transistor formed using an oxide semiconductor and having stable electric...
9006884 Three dimensional semiconductor device including pads  
A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first...
9006110 Method for fabricating patterned structure of semiconductor device  
A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two...
9006843 Source/drain extension control for advanced transistors  
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate...
9000527 Gate stack with electrical shunt in end portion of gate stack  
A semiconductor device is formed in which a first-type doped field effect transistor has a first gate stack that has an end portion with a second gate stack formed for a second-type, complementary...
9000525 Structure and method for alignment marks  
The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and...
9000535 Semiconductor device and semiconductor device manufacturing method  
A semiconductor device includes: a semiconductor substrate; a first transistor which is formed on the semiconductor substrate and includes a source/drain region and a gate electrode; an insulating...
9000526 MOSFET structure with T-shaped epitaxial silicon channel  
A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI...
9000528 Semiconductor device and fabrication method  
A semiconductor device using a small-sized metal contact as a program gate of an antifuse, and a method of fabricating the same are described. The semiconductor device includes a metal contact...
9000483 Semiconductor device with fin structure and fabrication method thereof  
A semiconductor device includes a substrate, a first fin structure, an electrical contact structure and a gate structure. The first fin structure includes a horizontal fin structure extending...
9000508 Nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein  
Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy...
8994114 Performance enhancement of active device through reducing parasitic conduction  
An apparatus having an active device, a plurality of traces and one or more areas is disclosed. The active device may have a channel layer. A buffer layer is generally disposed between the channel...
8994104 Contact resistance reduction employing germanium overlayer pre-contact metalization  
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a...
8994116 Hybrid gate process for fabricating FinFET device  
Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over...
8994113 Semiconductor device and method of manufacturing a semiconductor device  
A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A...
8994105 Power device integration on a common substrate  
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first...
8994115 Power device integration on a common substrate  
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first...
8994147 Semiconductor device and semiconductor element  
A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of...
8995177 Integrated circuits with asymmetric transistors  
Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data...
8994098 Semiconductor device including pillar transistors  
A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a...
8993392 Zener diode structure and process  
A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last...
8994112 Fin field effect transistor (finFET)  
A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper...
8987722 Self-aligned bottom-gated graphene devices  
A carbon-based semiconductor structure includes a substrate and a gate stack. The gate stack includes a carbon-based gate electrode formed on the substrate. The gate stack also includes a gate...
8987826 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work...