Patents in Class 257/346

Matches 1 - 50 out of 375

1 2 3 4 5 6 7 8 >

Match	Document	Document Title
1	9029834	Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is...
2	8994107	Semiconductor devices and methods of forming the semiconductor devices including a retrograde well Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain...
3	8952452	Semiconductor devices and method of manufacturing the same Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film...
4	8823095	MOS-power transistors with edge termination with small area requirement It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into...
5	8816328	Patterning contacts in carbon nanotube devices A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT...
6	8802514	Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device...
7	8803129	Patterning contacts in carbon nanotube devices A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further...
8	8796758	Selective epitaxial growth of semiconductor materials with reduced defects A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and...
9	8772168	Formation of the dielectric cap layer for a replacement gate structure Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure...
10	8766360	Insulative cap for borderless self-aligning contact in semiconductor device An apparatus comprises: a semiconductor device on a base substrate, the semiconductor device having a core metal positioned proximate a source and a drain in the base substrate; a work function...
11	8722500	Methods for fabricating integrated circuits having gate to active and gate to gate interconnects Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy...
12	8703611	Method for manufacturing a semiconductor structure A method for manufacturing a semiconductor structure is disclosed. The method comprises following steps. A substrate is provided. A sacrificial layer is formed on the substrate. The sacrificial...
13	8698207	Photodetector having a very thin semiconducting region The instant disclosure describes a photodetector that includes at least one portion of a semiconducting layer formed directly on at least a portion of a reflective layer and to be illuminated with...
14	8698243	Semiconductor device with strain-inducing regions and method thereof Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device...
15	8686499	Semiconductor device A semiconductor device includes a p-type semiconductor substrate, an n-type drift region formed in the p-type semiconductor substrate, and a p-type body region formed in the n-type drift region. A...
16	8680646	Self-aligned carbon electronics with embedded gate electrode A device and method for device fabrication include forming a buried gate electrode in a dielectric substrate and patterning a stack having a high dielectric constant layer, a carbon-based...
17	8674442	Semiconductor device and manufacturing method thereof A high voltage/power semiconductor device using a low voltage logic well is provided. The semiconductor device includes a substrate, a first well region formed by being doped in a first location...
18	8674438	Semiconductor devices having stressor regions and related fabrication methods Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying...
19	8664725	Strain enhanced transistors with adjustable layouts A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be...
20	8633485	Display device and manufacturing method thereof To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film...
21	8614486	Low resistance source and drain extensions for ETSOI A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment,...
22	8598661	Epitaxial process for forming semiconductor devices A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching...
23	8592280	Fin field effect transistor devices with self-aligned source and drain regions Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the...
24	8569121	Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device...
25	8531619	Active matrix liquid crystal display device with overlapping conductive film and pixel electrode A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source...
26	8525257	LDMOS transistor with asymmetric spacer as gate The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on...
27	8502314	Multi-level options for power MOSFETS This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the...
28	8502313	Double layer metal (DLM) power MOSFET This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least...
29	8471329	Tunnel FET and methods for forming the same A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is...
30	8426916	Semiconductor integrated circuit devices having different thickness silicon-germanium layers Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the...
31	8426283	Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate A method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate, in which, a substrate includes a first fin structure covered with a first mask layer and a second...
32	8368128	Compact field effect transistor with counter-electrode and fabrication method An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on...
33	8354711	Power MOSFET and its edge termination Improved MOSFET structures and processes, where multiple polysilicon embedded regions are introduced into the n+ source contact area. A top poly Field Plate is used to shield the electric field...
34	8343870	Semiconductor device and method of manufacturing the same A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect...
35	8338884	Selective epitaxial growth of semiconductor materials with reduced defects A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and...
36	8334560	Reverse disturb immune asymmetrical sidewall floating gate devices Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a...
37	8294238	Nonvolatile semiconductor memory device with reduced size of peripheral circuit area A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect...
38	8288805	Semiconductor device with gate-undercutting recessed region A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a...
39	8253163	High voltage semiconductor device including a free wheel diode A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region...
40	8248551	Semiconductor device including capacitor line parallel to source line A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source...
41	8217465	Semiconductor constructions In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are...
42	8217448	Semiconductor device and method of forming a semiconductor device A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a...
43	8217471	System and method for metal-oxide-semiconductor field effect transistor System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the...
44	8207030	Method for producing nMOS and pMOS devices in CMOS processing A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single...
45	8154079	Semiconductor device and fabrication method of the semiconductor device A semiconductor device, which can prevent an element breakdown by alleviating of electric field concentrations, and can also prevent reduction of gain, includes: a source electrode formed on a...
46	8143670	Self aligned field effect transistor structure Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on...
47	8138491	Self-aligned nanotube field effect transistor A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the...
48	8134152	CMOS thin film transistor, method of fabricating the same and organic light emitting display device having laminated PMOS poly-silicon thin film transistor with a top gate configuration and a NMOS oxide thin film transistor with an inverted staggered bottom gate configuration A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom...
49	8119487	Semiconductor device and method for fabricating the same A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well,...
50	8110866	Non-volatile memory device having asymmetric source/drain junction and method for fabricating the same Disclosed herein are non-volatile memory devices with asymmetric source/drain junctions and a method for fabricating the same. According to the method, a gate stack is formed on a semiconductor...

Matches 1 - 50 out of 375

1 2 3 4 5 6 7 8 >