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9041101 Power semiconductor device  
A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has...
9041100 Semiconductor device, and manufacturing method for same  
A semiconductor device has a source region, channel region, and drain region disposed in order from the surface of the device in the thickness direction of a semiconductor substrate. The device...
9035379 High voltage and ultra-high voltage semiconductor devices with increased breakdown voltages  
A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches...
9035375 Field-effect device and manufacturing method thereof  
Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region...
9035377 Semiconductor device  
A semiconductor device of an embodiment has a first conductive type first semiconductor layer, a second conductive type second semiconductor layer provided in the first semiconductor layer having...
9024381 Semiconductor device and fabricating method thereof  
A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super...
9024330 Semiconductor device and manufacturing method thereof  
A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming...
9025266 Semiconductor integrated circuit device, magnetic disk storage device, and electronic apparatus  
A semiconductor integrated circuit device has a p-type substrate to which a ground voltage is applied and a floating-type NMOSFET which is integrated on the p-type substrate and to which a...
9018062 Wafer structure and power device using the same  
In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping...
9012987 Semiconductor device, printing apparatus, and manufacturing method thereof  
A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first...
9013007 Semiconductor device having depletion type MOS transistor  
A depletion type MOS transistor includes a well region having a first conductivity type and formed on a semiconductor substrate, a gate insulating film formed on the well region, and a gate...
9006820 Vertical DMOS transistor  
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated...
9006825 MOS device with isolated drain and method for fabricating the same  
A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a...
9006707 Forming arsenide-based complementary logic on a single substrate  
In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium...
RE45449 Power semiconductor having a lightly doped drift and buffer layer  
A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped...
8994104 Contact resistance reduction employing germanium overlayer pre-contact metalization  
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a...
8994103 High voltage metal-oxide-semiconductor transistor device and manufacturing method thereof  
A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the...
8987810 Semiconductor device and method for fabricating the same  
A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate,...
8987820 Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same  
A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region...
8987816 Contact power rail  
A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active...
8987821 LDMOS with accumulation enhancement implant  
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device includes an enhancement implant region formed in a portion of an accumulation region proximate a P-N junction between...
8981477 Laterally diffused metal oxide semiconductor  
A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region...
8981474 Semiconductor device  
A semiconductor device formed on a silicon-on-insulator substrate includes a gate electrode, a gate insulation film, a drain diffusion region, a drift region, a body region, a plurality of source...
8981473 Dielectric isolation substrate and semiconductor device  
According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first...
8981475 Lateral diffusion metal oxide semiconductor (LDMOS)  
A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a...
8981472 MOS transistor and fabrication method of semiconductor integrated circuit device  
A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a...
8981476 Semiconductor device with high breakdown voltage and manufacture thereof  
A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type...
8975662 Method of manufacturing a semiconductor device using an impurity source containing a metallic recombination element and semiconductor device  
Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die....
8975693 Metal oxide semiconductor devices with multiple drift regions  
A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an...
8969161 Semiconductor device and method for fabricating semiconductor device  
A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction...
8969953 Method of forming a self-aligned charge balanced power DMOS  
Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity...
8963235 Trench power device and semiconductor structure thereof  
A semiconductor structure of a trench power device comprises a base, an insulating layer, and a source conductive layer. The base includes a first trench etched from the top surface thereof, and...
8957475 Bootstrap field effect transistor (FET)  
A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect...
8952455 Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit  
In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a...
8952553 Semiconductor device with stress relaxation during wire-bonding  
The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor...
8946769 Lateral devices containing permanent charge  
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges...
8941176 Integrated device with raised locos insulation regions and process for manufacturing such device  
An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in...
8932928 Power MOSFET structure and method  
A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a...
8928074 Vertical junction field effect transistors and diodes having graded doped regions and methods of making  
Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN...
8921933 Semiconductor structure and method for operating the same  
A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a...
8921934 FinFET with trench field plate  
An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad...
8921190 Field effect transistor and method of manufacture  
A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure...
8916931 LDMOS semiconductor device with parasitic bipolar transistor for reduced surge current  
An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type...
8916930 Trenched power semiconductor device and fabrication method thereof  
A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping...
8916440 Semiconductor structures and methods of manufacture  
Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect...
8916935 ESD clamp in integrated circuits  
A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region...
8916439 Method for forming dual gate insulation layers and semiconductor device having dual gate insulation layers  
Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first...
8916913 High voltage semiconductor device and the associated method of manufacturing  
The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial...
8907410 TSV structure with a built-in U-shaped FET transistor for improved characterization  
A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner...
8907419 LDMOS with enhanced safe operating area (SOA) and method therefor  
A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein...