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US20130246983 GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES  
A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having...
US20140173534 RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES  
In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the...
US20100325591 Generation and Placement Of Sub-Resolution Assist Features  
Sub-resolution assist features (SRAFs) are placed in a template form and in series adjacent to main features in a layout design. After each SRAF template is placed, a clean-up process is conducted...
US20140285272 Computer Aided Fabrication Systems  
A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor...
US20150121318 AUTOMATED GENERATION OF MASK FILE FROM THREE DIMENSIONAL MODEL FOR USE IN GRAYSCALE LITHOGRAPHY  
A method, apparatus and program product automatically generate a grayscale lithography mask file (76) from a three dimensional (3D) model (72) of a desired topography, e.g., as generated by a...
US20120042291 Inverse Mask Design and Correction for Electronic Design  
Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by...
US20110004856 Inverse Mask Design and Correction for Electronic Design  
Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by...
US20140195994 DEFECTIVE ARTIFACT REMOVAL IN PHOTOLITHOGRAPHY MASKS CORRECTED FOR OPTICAL PROXIMITY  
Defective artifact removal is described in photolithography masks corrected for optical proximity. In one example a method is described in which partitions are identified in a mask design for...
US20100138806 RESOLUTION ENHANCING TECHNOLOGY USING PHASE ASSIGNMENT BRIDGES  
In one embodiment, a spacing is determined for each edge of a number of features in a photolithographic design. The edges have at least a partially predictable layout. Based on the spacing and the...
US20140115546 Layout Design for Electron-Beam High Volume Manufacturing  
The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further...
US20150213182 COMMON TEMPLATE FOR ELECTRONIC ARTICLE  
One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first...
US20140282305 COMMON TEMPLATE FOR ELECTRONIC ARTICLE  
One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first...
US20130191796 INTEGRATED CIRCUIT LAYOUT MODIFICATION  
Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit,...
US20150227666 METHOD OF DECOMPOSING DESIGN LAYOUT FOR DOUBLE PATTERNING PROCESS  
A method of decomposing a design layout for a double patterning process is provided. The method includes changing, by a computing system, a design layout of a first polygon type to a design layout...
US20120102442 SYSTEM AND METHOD FOR MODEL BASED MULTI-PATTERNING OPTIMIZATION  
Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic...
US20120131522 METHOD FOR GENERATING ULTRA-SHORT-RUN-LENGTH DUMMY POLY FEATURES  
A method and apparatus for designing a lithography mask set which provides polygon features of a desired size at advanced technology nodes, for example, using live features and dummy features. A...
US20140380256 DOUBLE PATTERNING LAYOUT DESIGN METHOD  
A double patterning layout design method comprises defining critical paths comprising a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a...
US20130326438 LAYOUT MODIFICATION METHOD AND SYSTEM  
A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout,...
US20140181762 LITHOGRAPHY AWARE LEAKAGE ANALYSIS  
A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage...
US20120167021 Cell Layout for Multiple Patterning Technology  
A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During...
US20140082572 METHOD OF GENERATING ASSISTANT FEATURE  
A method of generating an assistant feature is provided. A plurality of main features is provided. A first main feature is selected from the main features. A plurality of rule-based features is...
US20120110524 METHODS, PHOTOMASKS AND METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE  
A method of improving damascene wire uniformity without reducing performance. The method includes simultaneously forming a multiplicity of damascene wires and a multiplicity metal dummy shapes in...
US20100333049 Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography  
Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations...
US20140047398 MASKS FOR DOUBLE PATTERNING PHOTOLITHOGRAPHY  
Improved masks for double patterning lithography are described. In one example, conflict spaces between features of a target design are identified. The conflict spaces are represented as nodes of...
US20110271240 METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT  
A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask...
US20110161907 Practical Approach to Layout Migration  
The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first...
US20110209107 MASK-LAYOUT CREATING METHOD, APPARATUS THEREFOR, AND COMPUTER PROGRAM PRODUCT  
According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the...
US20120124530 MAKING A DISCRETE SPATIAL CORRELATION CONTINUOUS  
A mechanism is provided for making a discrete spatial correlation on a 2D grid continuous. The region has given grid points and each of the grid points has its discrete stochastic variable....
US20110172110 TRACERS AND ASSEMBLY FOR LABELING CHEMICAL OR BIOLOGICAL MOLECULES METHODS AND KITS USING THE SAME  
An improved process to create an arbitrarily large number of distinguishable particles allows more flexibility in experimental design and related efficiencies of scale. Novel enhanced tracers, for...
US20130290914 Methods and Apparatus for Floorplanning and Routing Co-Design  
Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may...
US20070266365 Integrated Circuit Design Meethod, Design Assistance Program and Integrated Circuit Design System Using Such Integrated Circuit Design Method  
[PROBLEMS] To provide an integrated circuit design method realized as a photomask/photomaskless fusion method wherein a photomask trial method and a photomaskless trial method are fused with each...
US20110143268 Scattering Bar OPC Application Method for Sub-Half Wavelength Lithography Patterning  
A method of forming a mask having optical proximity correction features, which includes the steps of obtaining a target pattern of features to be imaged, expanding- the width of the features to be...
US20120216157 ROUTING ANALYSIS WITH DOUBLE PATTERN LITHOGRAPHY  
Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are...
US20090187878 DATA GENERATION METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRON BEAM EXPOSURE SYSTEM  
A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference...
US20140199844 ARRAY DESCRIPTION SYSTEM FOR LARGE PATTERNS  
A method for describing an array of elements includes the steps of providing an array description system that includes a library of possible alternative designations; and describing the array of...
US20140359544 LAYOUT RE-DECOMPOSITION FOR MULTIPLE PATTERNING LAYOUTS  
Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are...
US20070006117 Method for optimally converting a circuit design into a semiconductor device  
A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design...
US20110033787 FRAME CELL FOR SHOT LAYOUT FLEXIBILITY  
A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An...
US20130332893 FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM  
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a...
US20110078639 FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM  
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a...
US20120017184 SYSTEM FOR CREATING LAYOUT PATTERN FOR MANUFACTURING MASK ROM, MASK ROM MANUFACTURED USING THE SYSTEM, AND METHOD FOR CREATING MASK PATTERN  
When generating a temporary ROM code file and a design information file, a host server generates a dedicated ROM compiler and an intermediate file associated with the dedicated ROM compiler. In a...
US20150040082 LAYOUT DECOMPOSITION METHOD  
A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design....
US20140152947 MANUFACTURING DEVICE FOR LIQUID CRYSTAL PANEL AND LIQUID CRYSTAL PANEL  
The manufacturing device for a liquid crystal panel which has a non-displaying area includes a two-dimensional code generating module configured for generating a rectangle-shaped two-dimensional...
US20080179713 Etching Technique For Creation of Thermally-Isolated Microstructures  
There is described a method for creating a thermally-isolated microstructure on a slab of mono-crystalline silicon which uses a hybrid dry-then-wet etch technique that when controlled, can produce...
US20110252387 METHOD AND APPARATUS FOR REDUCING IMPLANT TOPOGRAPHY REFLECTION EFFECT  
Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a...
US20130311960 METHOD AND APPARATUS FOR ENHANCING SIGNAL STRENGTH FOR IMPROVED GENERATION AND PLACEMENT OF MODEL-BASED SUB-RESOLUTION ASSIST FEATURES (MB-SRAF)  
Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of...
US20110173578 Method and Apparatus for Enhancing Signal Strength for Improved Generation and Placement of Model-Based Sub-Resolution Assist Features (MB-SRAF)  
Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of...
US20140007026 LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS  
A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the...
US20120196230 LAYOUT DECOMPOSITION METHOD AND APPARATUS FOR MULTIPLE PATTERNING LITHOGRAPHY  
An initial layout of at least a portion of a given layer of an integrated circuit design is decomposed into multiple sub-layouts by splitting each of a plurality of shapes of the initial layout...
US20130074018 MULTI-PATTERNING METHOD  
A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed...