Matches 1 - 50 out of 188 1 2 3 4 >


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US20100325591 Generation and Placement Of Sub-Resolution Assist Features  
Sub-resolution assist features (SRAFs) are placed in a template form and in series adjacent to main features in a layout design. After each SRAF template is placed, a clean-up process is conducted...
US20120102440 METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES  
Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement...
US20120096414 METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES  
Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement...
US20150082260 MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING  
Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer...
US20150161320 SCATTERING BAR OPTIMIZATION APPARATUS AND METHOD  
A computer-implemented method is disclosed for optimizing one or more sub-resolution assist features for use in a photolithographic process. The method may include incorporating a sub-resolution...
US20120210281 FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS  
A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected...
US20120036487 FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS  
A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected...
US20080034332 Optimization Of Geometry Pattern Density  
Techniques are provided for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define fill regions that can be filled with...
US20070256046 Analysis and optimization of manufacturing yield improvements  
Techniques for improving the design of circuits, such as integrated microcircuits. A proposed circuit design is analyzed to identify design features associated with yield loss in manufactured...
US20140068530 FAST FREEFORM SOURCE AND MASK CO-OPTIMIZATION METHOD  
The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and...
US20150048457 Mask Optimization for Multi-Layer Contacts  
A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated...
US20070256039 DUMMY FILL FOR INTEGRATED CIRCUITS  
Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the...
US20130042212 Multivariable Solver for Optical Proximity Correction  
The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a...
US20130174104 PLACEMENT AWARE CLOCK GATE CLONING AND FANOUT OPTIMIZATION  
Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to...
US20070006117 Method for optimally converting a circuit design into a semiconductor device  
A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design...
US20130198696 METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS  
A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated...
US20140068529 SOLUTIONS FOR RETARGETING INTEGRATED CIRCUIT LAYOUTS BASED ON DIFFRACTION PATTERN ANALYSIS  
A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a...
US20140143742 Design, Layout, and Manufacturing Techniques for Multivariant Integrated Circuits  
An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of...
US20130091475 Polarization Monitoring Reticle Design for High Numerical Aperture Lithography Systems  
This invention relates to the manufacture of semiconductor substrates such as wafers and to a method for monitoring the state of polarization incident on a photomask in projection printing using a...
US20130219350 REDUCE MASK OVERLAY ERROR BY REMOVING FILM DEPOSITED ON BLANK OF MASK  
A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask...
US20060206851 Determning lithographic parameters to optimise a process window  
For determining best process variables (E, F, W) setting that provide optimum process window for a lithographic process for printing features having critical dimensions (CD) use is made of an...
US20130036390 Layout Content Analysis for Source Mask Optimization Acceleration  
The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the...
US20060253810 Integrated circuit design to optimize manufacturability  
Library design elements (102) are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a...
US20140101625 DESIGN RULE OPTIMIZATION IN LITHOGRAPHIC IMAGING BASED ON CORRELATION OF FUNCTIONS REPRESENTING MASK AND PREDEFINED OPTICAL CONDITIONS  
Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination...
US20150234970 SYNTHESIZING LOW MASK ERROR ENHANCEMENT FACTOR LITHOGRAPHY SOLUTIONS  
In one embodiment, a source mask optimization (SMO) method is provided that includes controlling bright region efficiency during at least one optical domain step. The bright region efficiency...
US20080178142 Hotspot detection method for design and validation of layout for semiconductor device  
A hotspot detection method for detecting a hotspot in a layout for a semiconductor device, includes: dividing a target analysis area into a grid based on layout data about the semiconductor...
US20090296055 LENS HEATING COMPENSATION SYSTEMS AND METHODS  
Methods for calibrating a photolithographic system are disclosed. A cold lens contour for a reticle design and at least one hot lens contour for the reticle design are generated from which a...
US20120260223 Retargeting for Electrical Yield Enhancement  
A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set...
US20130326437 GRADIENT-BASED PATTERN AND EVALUATION POINT SELECTION  
Described herein is a method for a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic imaging apparatus, the lithographic process having a...
US20050229145 Method and system for chrome cut-out regions on a reticle  
A method and system for chrome cut-out regions on a reticle is described. The method includes determining a location of one or more regions on a reticle that come in contact with a reticle...
US20070266360 Metal Thickness Simulation for Improving RC Extraction Accuracy  
An integrated circuit (IC) design method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a...
US20090077524 METHOD OF MANUFACTURING PHOTOMASK  
A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level...
US20080155482 AUTOMATED OPTIMIZATION OF VLSI LAYOUTS FOR REGULARITY  
VLSI lithographic fidelity is improved via reducing the pattern space of difficult patterns or structures in a design layout for an integrated circuit design, and thereby increasing the regularity...
US20060190850 Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask  
A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns....
US20150074622 OPTIMIZATION OF SOURCE, MASK AND PROJECTION OPTICS  
Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a...
US20120117522 Optimization of Source, Mask and Projection Optics  
Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a...
US20070266346 Method of Design For Manufacturing  
Disclosed is a system and method for enhancing integrated circuit designs and predicting the manufacturability. Design for manufacturability, or DFM, is an integration of DFM advisories; a DFM...
US20070006113 Determining an optimizaton for generating a pixelated photolithography mask with high resolution imaging capability  
A pixelated photolithography mask is optimized for high resolution microelectronic processing. In one embodiment, the invention includes synthesizing a pixelated photolithography mask, applying a...
US20150082259 LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN  
A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other...
US20070281218 Dummy Phase Shapes To Reduce Sensitivity Of Critical Gates To Regions Of High Pattern Density  
A method of generating dummy phase shapes in the layout of an alternating phase shift mask. The method comprises identifying a linewidth-sensitive feature and a large feature in the circuit...
US20110173577 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields  
Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following...
US20150186582 METHOD AND APPARATUS FOR DESIGN OF A METROLOGY TARGET  
A method of metrology target design is described. The method includes providing a range or a plurality of values for design parameter of a metrology target and by a processor, selecting, by...
US20140033145 PATTERN-DEPENDENT PROXIMITY MATCHING/TUNING INCLUDING LIGHT MANIPULATION BY PROJECTION OPTICS  
Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing...
US20120117521 Pattern-Dependent Proximity Matching/Tuning Including Light Manipulation By Projection Optics  
Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing...
US20120102441 MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS  
A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system...
US20060085773 Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity  
An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield...
US20130263064 METHODS AND SYSTEM FOR MODEL-BASED GENERIC MATCHING AND TUNING  
The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a...
US20150058816 METHOD FOR INTEGRATED CIRCUIT DESIGN LAYOUT SUPPORT BY COMPUTER AND APPARATUS OF INTEGRATED CIRCUIT DESIGN LAYOUT SUPPORT BY COMPUTER  
According to one embodiment, a method is disclosed for designing an integrated circuit by a computer including an input unit, a memory unit, a calculating unit, and an output unit. The method can...
US20110099526 Pattern Selection for Full-Chip Source and Mask Optimization  
The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and...
US20100269084 Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography  
Kernels that model characteristics of the etching portion of an optical lithographic model are provided. In various implementations, a visibility density kernel is provided. The visibility density...

Matches 1 - 50 out of 188 1 2 3 4 >