Matches 1 - 50 out of 195 1 2 3 4 >

AcclaimIP-ad

Match Document Document Title
US20120107729 GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES  
A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having...
US20110179391 LEAKAGE AWARE DESIGN POST-PROCESSING  
The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is...
US20110154280 PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY  
An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape...
US20090181314 Reverse Dummy Insertion Algorithm  
A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a...
US20100005440 CALIBRATION AND VERIFICATAION STRUCTURES FOR USE IN OPTICAL PROXIMITY CORRECTION  
A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a...
US20100332206 METHOD FOR SIMULATING LEAKAGE DISTRIBUTION OF INTEGRATED CIRCUIT DESIGN  
A method is provided for simulating leakage distribution of integrated circuit design. The method analyzes a layout of the integrated circuit design to understand the groups of dimensions of the...
US20110057282 PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL  
CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in...
US20090037866 ALTERNATING PHASE SHIFT MASK OPTIMIZATION FOR IMPROVED PROCESS WINDOW  
A method for designing alternating phase shift masks is provided, in which narrow phase shapes located between densely spaced design shapes are colored to allow a maximum amount of light...
US20100333049 Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography  
Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations...
US20090100399 DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS  
A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim...
US20120005633 CONSISTENCY CHECK IN DEVICE DESIGN AND MANUFACTURING  
A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an...
US20110161907 Practical Approach to Layout Migration  
The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first...
US20110131538 METHOD FOR DESIGNING TWO-DIMENSIONAL ARRAY OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERRORS USING THE SAME  
A method for designing a two-dimensional array overlay target comprises the steps of: selecting a plurality of two dimensional array overlay targets having different overlay errors; calculating a...
US20110154272 METHOD FOR DESIGNING TWO-DIMENSIONAL ARRAY OVERLAY TARGET SETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERRORS USING THE SAME  
A method for designing a two-dimensional array overlay target set comprises the steps of: selecting a plurality of two-dimensional array overlay target sets having different overlay errors;...
US20110252387 METHOD AND APPARATUS FOR REDUCING IMPLANT TOPOGRAPHY REFLECTION EFFECT  
Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a...
US20130072020 Method For Ensuring DPT Compliance for Auto-Routed Via Layers  
A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming...
US20120180005 LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL  
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors....
US20070261016 Masking techniques and templates for dense semiconductor fabrication  
A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is formed using pitch multiplication...
US20130086534 METHOD FOR DETERMINING WIRE LENGTHS BETWEEN NODES USING A RECTILINEAR STEINER MINIMUM TREE (RSMT) WITH EXISTING PRE-ROUTES ALGORITHM  
A method for the creation of rectilinear Steiner minimum trees includes determining a set of candidate connections from a terminal node to a different terminal node or to a graph edge. The length...
US20080195995 FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES  
Structures and methods for forming the same. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features....
US20090220868 MASK AND DESIGN METHOD THEREOF  
A mask and the design method thereof are provided. The mask includes a light-shielding area shielding off a light, wherein the light-shielding area includes a photonic crystal having a lattice...
US20090132992 STATISTICAL OPTICAL PROXIMITY CORRECTION  
An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct...
US20090296055 LENS HEATING COMPENSATION SYSTEMS AND METHODS  
Methods for calibrating a photolithographic system are disclosed. A cold lens contour for a reticle design and at least one hot lens contour for the reticle design are generated from which a...
US20110138342 Retargeting for Electrical Yield Enhancement  
A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set...
US20080320435 OPTICAL PROXIMITY CORRECTION IMPROVEMENT BY FRACTURING AFTER PRE-OPTICAL PROXIMITY CORRECTION  
A method for fabricating a mask used to make integrated circuits is provided using an improved OPC process whereby a pre-fracturing OPC process is performed on the target design of the integrated...
US20090075183 Technique for Determining Mask Patterns and Write Patterns  
During a method for generating a third mask pattern to be used on a photo-mask in a photolithographic process, first features are added to a first mask pattern to produce a second mask pattern. A...
US20120167018 Method for Decomposing a Designed Pattern Layout  
A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality...
US20110197168 DECOMPOSING INTEGRATED CIRCUIT LAYOUT  
Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout...
US20100242012 FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES  
A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method...
US20090243022 METHOD OF FORMING MASK FOR LITHOGRAPHY, METHOD OF FORMING MASK DATA FOR LITHOGRAPHY, METHOD OF MANUFACTURING BACK-ILLUMINATED SOLID-STATE IMAGING DEVICE, BACK-ILLUMINATED SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE  
A method of forming a mask for lithography includes the step of forming the mask by using reverse data in which positions of at least part of output terminals are reversed, when forming the mask...
US20140078479 IMAGE OPTIMIZATION USING PUPIL FILTERS IN PROJECTING PRINTING SYSTEMS WITH FIXED OR RESTRICTED ILLUMINATION ANGULAR DISTRIBUTION  
A pupil filter can be designed for any combination of an illumination lens and for various types of lithographic features. The pupil filter can be placed at the pupil plane of a projection optics...
US20110119642 Simultaneous Photolithographic Mask and Target Optimization  
A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more...
US20110029939 METHOD FOR CORRECTING LAYOUT PATTERN  
A method for correcting layout pattern is disclosed. The method includes the steps of: providing a layout pattern having at least one segment; forming a rule-checking rectangle from the segment,...
US20090077524 METHOD OF MANUFACTURING PHOTOMASK  
A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level...
US20090187876 STEINER TREE BASED APPROACH FOR POLYGON FRACTURING  
Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points...
US20080282218 Method for Designing Mask  
A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern...
US20140351771 SCATTEROMETRY OVERLAY METROLOGY TARGETS AND METHODS  
Scatterometry overlay (SCOL) targets as well as design, production and measurement methods thereof are provided. The SCOL targets have several periodic structures at different measurement...
US20110209106 METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY  
A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening...
US20100065913 Performance-Aware Logic Operations for Generating Masks  
A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first...
US20060266833 System, method and computer software product for inspecting charged particle responsive resist  
A system, computer software product and a method for evaluating a mask, the method includes the stages of: defining multiple CD measurement target windows; defining multiple pattern recognition...
US20100064273 Method for Compensating for Variations in Structures of an Integrated Circuit  
A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b)...
US20130298088 System and Method for Combined Intraoverlay and Defect Inspection  
A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving...
US20110114949 TEST CHIPLETS FOR DEVICES  
A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a...
US20110079779 SHAPE CHARACTERIZATION WITH ELLIPTIC FOURIER DESCRIPTOR FOR CONTACT OR ANY CLOSED STRUCTURES ON THE CHIP  
Shapes and orientations of contacts or other closed contours on an integrated circuit are characterized by calculating Elliptic Fourier descriptors. The descriptors are then used for generating...
US20090007051 SELECTABLE DEVICE OPTIONS FOR CHARACTERIZING SEMICONDUCTOR DEVICES  
A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system...
US20080313593 Occupancy Based on Pattern Generation Method For Maskless Lithography  
An occupancy based pattern generation method for a maskless lithography system using micromirrors is disclosed. The present invention includes the steps of recognizing a pattern upon the substrate...
US20090233187 Designing method of photo-mask and method of manufacturing semiconductor device using the photo-mask  
In a method of designing a photo-mask, a graphic pattern as a target of development simulation is divided into a plurality of sub graphic patterns which are respectively assigned with a plurality...
US20100042967 MEEF REDUCTION BY ELONGATION OF SQUARE SHAPES  
A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the...
US20110004854 Method for Fabricating Assist Features in a Photomask  
Disclosed is a method of fabricating an assist feature in a photomask, which includes: fabricating a design layout in which main patterns are arranged; setting a critical dimension (a) of assist...
US20110271239 Lithography Performance Check Methods and Apparatus  
The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design...
Matches 1 - 50 out of 195 1 2 3 4 >