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US20140215426 ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS WITH VARYING GRID DENSITIES  
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for...
US20130326458 TIMING REFINEMENT RE-ROUTING  
A design tool can automatically improve timing of nets of a fully routed physical design solution. Nets of a netlist are evaluated against a plurality of re-routing criteria to identify the nets...
US20110055784 MULTI-THREADED GLOBAL ROUTING  
Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During...
US20120110537 METHODS AND SYSTEMS FOR FLEXIBLE AND REPEATABLE PRE-ROUTE GENERATION  
Methods and systems for flexible and repeatable pre-route generation are described. In one embodiment, a routing selection is received. The routing selection is for a path between at least a first...
US20120102446 IMPLEMENTING NET ROUTING WITH ENHANCED CORRELATION OF PRE-BUFFERED AND POST-BUFFERED ROUTES  
A method, system and computer program product are provided for implementing enhanced net routing with improved correlation of pre-buffered and post-buffered routes on a hierarchical design of an...
US20140289693 SYSTEM AND METHOD FOR IMPROVED NET ROUTING  
An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a shape with a perimeter; offsetting at least a part of a segment of the perimeter of the shape from...
US20140059509 METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE  
A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a...
US20140189630 SOFT PIN INSERTION DURING PHYSICAL DESIGN  
A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at...
US20130086545 EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTION HISTOGRAMS  
Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying...
US20100146473 ROUTING SYSTEM  
A process for shortest path routing in computer-aided designs (CAD) is performed using an incremental graph traversal technique. This technique searches the shortest path routing trees in a graph...
US20120180017 ROUTING G-BASED PIN PLACEMENT  
A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline,...
US20110126165 SYSTEM AND PROCESS FOR CLIENT DRIVEN AUTOMATED CIRCUITING AND BRANCH CIRCUIT WIRING  
A computer aided design application modifies a CAD drawing having one or more electrical components by optimizing a plurality of circuits and associated panels, and assigning circuit and panel...
US20130227511 METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING  
In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated...
US20120284683 TIMING DRIVEN ROUTING IN INTEGRATED CIRCUIT DESIGN  
A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a...
US20110276936 METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY  
A method for analog placement and global routing considering wiring symmetry performs a layout for a circuit which is described by a netlist having a set of devices and wires. First, the method...
US20140223397 Automatic Generation of Wire Tag Lists for a Metal Stack  
Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack...
US20130097575 Rescaling  
A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes...
US20110302544 POST-PLACEMENT CELL SHIFTING  
A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles....
US20140252644 MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS  
Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design...
US20120174052 ROUTING  
A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation;...
US20110113400 METHOD OF MAKING IN AN INTEGRATED CIRCUIT INCLUDING SIMPLIFYING METAL SHAPES  
A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the...
US20070204255 Net routing  
A solution for routing a net based on a slew and/or delay for one or more critical sinks in the net is provided. To this extent, the solution can generate electrical connection information for a...
US20110113399 Methods and Systems for Optimizing Designs of Integrated Circuits  
Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a...
US20130270693 Trace Layout Method in Bump-on-Trace Structures  
A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process...
US20120110536 STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION  
An integrated circuit design is routed by first creating temporary routes in a flattened layout, generating blockage information for sub-blocks in the layout based on the temporary routes, and...
US20140327471 STANDARD CELLS FOR PREDETERMINED FUNCTION HAVING DIFFERENT TYPES OF LAYOUT  
An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending...
US20100146472 ROUTING SYSTEM  
A routing system is improved by performing three steps sequentially to complete an execution process. The first step estimates a normalized criticality score for each design net. The second step...
US20150067632 EFFICIENT ANALOG LAYOUT PROTOTYPING BY LAYOUT REUSE WITH ROUTING PRESERVATION  
A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a...
US20110029945 NetList Maintenance in a Circuit Diagram  
Maintaining a netlist while editing a circuit diagram. The circuit diagram may be displayed on a display. The circuit diagram may include a plurality of electronic components connected by nets and...
US20080276213 Method of shield line placement for semiconductor integrated circuit, design apparatus for semiconductor integrated circuit, and design program for semiconductor integrated circuit  
A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line...
US20090210849 Accurate Parasitics Estimation for Hierarchical Customized VLSI Design  
Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source...
US20130086544 CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL ROUTING  
Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the...
US20130086534 METHOD FOR DETERMINING WIRE LENGTHS BETWEEN NODES USING A RECTILINEAR STEINER MINIMUM TREE (RSMT) WITH EXISTING PRE-ROUTES ALGORITHM  
A method for the creation of rectilinear Steiner minimum trees includes determining a set of candidate connections from a terminal node to a different terminal node or to a graph edge. The length...
US20110276937 Integrated Circuit Routing with Compaction  
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel,...
US20130104095 Integrated Circuit Routing with Compaction  
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow...
US20120290997 Multi-Threaded Global Routing  
A method is described for routing a semiconductor chip's global nets. The method includes identifying a subset of the global nets and routing the subset of global nets using multiple threads,...
US20110145776 OPERATIONAL CYCLE ASSIGNMENT IN A CONFIGURABLE IC  
Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the...
US20080209384 Method of searching for wiring route in integrated circuit, automatic wiring device for integrated circuit, and program therefor  
A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been...
US20120017193 LAYOUT SYSTEM AND METHOD OF DIFFERENTIAL PAIR OF PRINTED CIRCUIT BOARD  
A layout method of a differential pair generates the differential pair between a differential signal sender and a differential signal receiver in a printed circuit board (PCB). Differential signal...
US20090271755 Unified Layer Stack Architecture  
A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced....
US20110304052 POWER GRID OPTIMIZATION  
A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may...
US20100262944 OBJECT PLACEMENT IN INTEGRATED CIRCUIT DESIGN  
A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the...
US20150054592 ON-CHIP VERTICAL THREE DIMENSIONAL MICROSTRIP LINE WITH CHARACTERISTIC IMPEDANCE TUNING TECHNIQUE AND DESIGN STRUCTURES  
A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically,...
US20120240093 ROUTING AND TIMING USING LAYER RANGES  
A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an...
US20080141208 Layout method of semiconductor integrated circuit and computer readable storage medium storing layout program thereof  
The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is...
US20080115099 Spatial curvature for multiple objective routing  
Spatial curvature techniques for multiple objective routing is described. In one or more embodiments, routing between components of an integrated circuit may be determined by transforming pin...
US20080148213 ROUTING METHOD FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT  
A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between...
US20090172629 Validating continuous signal phase matching in high-speed nets routed as differential pairs  
Methods and apparatus to validate continuous signal phase matching in high-speed nets routed as differential pairs are described. In one embodiment, a primary net of a differential pair may be...
US20050076319 Pin assignment in block-based integrated circuit design methodologies  
In pin assignment for blocks in a netlist, each one of a plurality of pins are first assigned to a respective one of a plurality of first locations along a periphery a block in accordance with...
US20090113373 Layout design apparatus, layout design method, and computer product  
A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout...

Matches 1 - 50 out of 141 1 2 3 >