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US20060168552 |
Substrate mapping
A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach... |
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US20160087635 |
Operational Time Extension
Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The... |
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US20130031524 |
ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for... |
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US20050268269 |
Methods and systems for cross-probing in integrated circuit design
When designing integrated circuits, RTL source code is received and converted into objects. Objects may include a reference to relevant lines of source RTL code. A graphical user interface (“GUI”)... |
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US20090184733 |
LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors.... |
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US20060206848 |
Method and apparatus for considering diagonal wiring in placement
The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of... |
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US20070101303 |
Method and apparatus for integrated circuit layout optimization
A method and apparatus for integrated circuit layout optimization are provided. In the conventional art, the major challenges in building integrated circuits (IC) at sub-wavelength geometries... |
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US20060190893 |
Logic cell layout architecture with shared boundary
Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method (200) for designing a logic cell library having a shared boundary... |
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US20110145775 |
CELL LIBRARY, LAYOUT METHOD, AND LAYOUT APPARATUS
In a cell library that is used for layout design of a semiconductor integrated circuit and is a library of design data of cells each realizing a unit function, each of the design data includes... |
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US20060101367 |
Design method of semiconductor device and semiconductor device
In an error analysis step, analysis of an antenna effect error, a timing constraint violation and the like is performed for layout data in which redundant via conversion has been performed. Then,... |
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US20080178135 |
CELLS OF INTEGRATED CIRCUIT AND RELATED TECHNOLOGY AND METHOD
Electronic cells/cell library and related technology/method capable of achieving high integration of integrated circuits. In one embodiment, the proposed technology adopts cells with cell heights... |
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US20080229269 |
DESIGN STRUCTURE FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES
A design structure embodied in a machine readable medium used in a design process includes a nonvolatile static random access memory (SRAM) device, including a pair of cross-coupled, complementary... |
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US20070050743 |
Vertical Twist Scheme for High Density DRAMs
An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and... |
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US20100148218 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME
The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the... |
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US20090193384 |
SHIFT-ENABLED RECONFIGURABLE DEVICE
A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array... |
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US20050132318 |
Layout quality analyzer
In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route... |
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US20060156267 |
Recording medium recording a wiring method
It is determined whether a short-run rule can be adapted into a position, where a via cell is parallel and adjacent to a portion of wiring or another via cell. The via cell and the portion of the... |
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US20080024173 |
Semiconductor integrated circuit including a malfunction detection circuit, and a design method for the same
A malfunction detection circuit realized by a simple circuit structure is incorporated into a semiconductor integrated circuit without increasing the scale thereof, in order to prevent loss etc.... |
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US20080244476 |
System and method for simultaneous optimization of multiple scenarios in an integrated circuit design
The present invention provides a system and method for concurrently performing analysis and optimization of an integrated circuit (IC) design in multiple scenarios. The system is based on a... |
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US20060117283 |
Integrated circuit verification method, verification apparatus, and verification program
A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical... |
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US20100058274 |
FLEXIBLE HARDWARE UPGRADE MECHANISM FOR DATA COMMUNICATIONS EQUIPMENT
Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial... |
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US20090007048 |
DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a... |
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US20050155001 |
Method for designing a semiconductor integrated circuit and a semiconductor integrated circuit
A method for designing a semiconductor integrated circuit, includes placing first, second and third cells, respectively including first stage synchronous circuit having signal propagation time,... |
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US20130095650 |
System And Method For Constructing Waffle Transistors
Waffle transistors are used within an integrated circuit when a transistor must carry an amount of current greater than the amount of current carried by a typical transistor in the integrated... |
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US20050097496 |
High-speed and low-power logical unit
It is an object of the present invention to provide a high-speed and low-power logical unit formed of a master slice integrated circuit, which offers advantages of reducing the cost and time... |
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US20050262464 |
Integrated circuit routing resource optimization algorithm for random port ordering
A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which... |
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US20100037197 |
Method and apparatus for integrated circuit design
An integrated circuit design method includes: obtaining layout data of an integrated circuit; and updating the layout data to modify the layout of the integrated circuit. In updating the layout... |
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US20090094570 |
Configurable Asic-based Sensing Circuit
A sensing circuit based on an application-specific integrated circuit (ASIC) sensor which includes a sensor portion and a processor portion which are integrated on an ASIC. The sensor portion... |
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US20110093827 |
SEMICONDUCTOR DEVICE DESIGN METHOD
There is provided a semiconductor device design method capable of achieving optimal layout design. For example, from the entire semiconductor device, a plurality of seeds which are flip-flops are... |
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US20090327989 |
Statistical Interconnect Corner Extraction
Various implementations of the invention provide methods and apparatuses that consider various inter/intra-die variations. In various implementations, a statistical parameter dimension reduction... |
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US20070162880 |
Single event transient immune antenna diode circuit
An antenna diode circuit is described. The antenna diode circuit includes two diodes connected in series between a signal line and ground. Alternatively, the antenna diode circuit is connected in... |
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US20050071797 |
Automatic layout system, layout model generation system, layout model verification system, and layout model
An automatic layout system generates a layout of a semiconductor device by placing cell layouts each configured to perform a specific function and providing a routing among the cell layouts. The... |
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US20070180420 |
Designing a circuit apparatus with multiple propagation speeds of signals
Designing a circuit apparatus involves determining locations and lengths of routing paths for signals, routing paths of a first length range being located in a first layer, and routing paths of a... |
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US20050172253 |
Automatic placement and routing device, method for placement and routing of semiconductor device, semiconductor device and manufacturing method of the same
A method of placement and routing of a semiconductor device, includes steps (a) to (c). The step (a) is a procedure of executing placement of functional blocks and executing routing of... |
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US20140144691 |
METHOD FOR SHORTENING VIA STUB AND PRINTED CIRCUIT BOARD DESIGNED BASED ON THE METHOD
A method for shortening a via stub includes: designing a first via hole to connect signal lines of a top layer and a bottom layer of a printed circuit board; and designing a second via hole to... |
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US20140111274 |
PROGRAMMABLE REVISION CELL ID SYSTEM AND METHOD
An integrated circuit comprising a plurality of metal programmable revision identification (MPRI) cells, wherein each MPRI cell further comprises a plurality of metal layers, a plurality of vias... |
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US20060259891 |
System and method of generating an auto-wiring script
A system and method of generating an auto-wiring script, which can be utilized to generate a script used exclusively for the wiring software according to corresponding table specifying the... |
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US20050183052 |
Computer-implemented design tool for synchronizing mechanical and electrical wire harness designs
A computer-implemented design tool is provided for analyzing a wire harness design for an electrical systems. The design tool includes: a synchronizing rule set residing in a data store; and a... |
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US20110289472 |
LAYOUT QUALITY EVALUATION
A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at... |
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US20090212818 |
Integrated circuit design method for improved testability
An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a... |
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US20120005643 |
System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width
Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal... |
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US20100234973 |
PATTERN VERIFYING METHOD, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND PATTERN VERIFYING PROGRAM
A specification of a layout of a layout pattern arranged on a layer is set based on three-dimensional structures of layers of a semiconductor integrated circuit. It is verified whether a layout... |
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US20110068423 |
PHOTODETECTOR WITH WAVELENGTH DISCRIMINATION, AND METHOD FOR FORMING THE SAME AND DESIGN STRUCTURE
The disclosure relates generally to photodetectors and methods of forming the same, and more particularly to optical photodetectors. The photodetector includes a waveguide having a radius that... |
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US20100229139 |
SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
An extraction unit extracts a metal pattern constituting a semiconductor integrated circuit from layout data. A setting unit sets up a region including the metal pattern extracted by the... |
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US20100235803 |
Method and Apparatus for Automatically Connecting Component Interfaces in a Model Description
The Component Interface Definition Language (CIDL) disclosed in this document, along with the associated CIDL compiler, provides advantageous automation and simplification of the process of... |
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US20110107291 |
DESIGN SYSTEM AND METHOD THAT, DURING TIMING ANALYSIS, COMPENSATES FOR REGIONAL TIMING VARIATIONS
Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such... |
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US20090019404 |
METHOD FOR CALCULATING DIFFICULTY LEVEL OF ROUTING IN NETLIST
The invention provides a method capable of calculating a difficulty level of routing at a high processing speed with good calculating accuracy. The method involves: performing hierarchical... |
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US20110154277 |
METHOD AND APPARATUS FOR GENERATING SUBSTRATE LAYOUT
Embodiments of the invention discuss methods and apparatus for efficiently generating substrate layout for motherboards and packages having high pin-count processors. The method comprises:... |
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US20100175038 |
Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design
A technique for implementing an engineering change order (ECO) includes comparing a first hardware description language (HDL) design with a second HDL design. In this case, the second HDL design... |
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US20090288057 |
System and Method for Ordering the Selection of Integrated Circuit Chips
A routing engine for use with a mounter having a chip selector and a method of routing a chip selector of a mounter. In one embodiment, the routing engine includes: (1) a memory configured to... |