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US20110035713 CIRCUIT BOARD DESIGN SYSTEM AND METHOD  
A method and system for designing a circuit board designs wiring of the circuit board, and determines electronic rules and physical rules of the wiring design. The method and system creates a...
US20150193572 TRACE ROUTING ACCORDING TO FREEFORM SKETCHES  
Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within...
US20110010683 Trace Routing According To Freeform Sketches  
Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within...
US20080141207 Wiring Design System of Semiconductor Integrated Circuit, Semiconductor Integrated Circuit, and Wiring Design Program  
A wiring design system for semiconductor integrated circuit which realizes a low power consumption in a grid-shaped clock wiring within a semiconductor integrated circuit is provided. A wiring...
US20110066989 METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS  
A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the...
US20110029944 ROUTING VARIANTS IN ELECTRONIC DESIGN AUTOMATION  
Some embodiments provide a system that facilitates the creation of a schematic in an electronic design automation (EDA) application. During operation, the system obtains a source point and a...
US20150026656 UPDATING PIN LOCATIONS IN A GRAPHICAL USER INTERFACE OF AN ELECTRONIC DESIGN AUTOMATION TOOL  
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an...
US20130031524 ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS  
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for...
US20110041112 METHOD AND APPARATUS FOR GENERATING A CENTERLINE CONNECTIVITY REPRESENTATION  
Some embodiments provide a system for generating a centerline connectivity representation for a set of routing shapes. During operation, the system can represent the set of routing shapes using a...
US20110055786 METHOD AND APPARATUS FOR SATISFYING ROUTING RULES DURING CIRCUIT DESIGN  
One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a...
US20140033155 SYSTEMS AND METHODS FOR GENERATING A HIGHER LEVEL DESCRIPTION OF A CIRCUIT DESIGN BASED ON CONNECTIVITY STRENGTHS  
Provided are systems and methods for generating a higher level description of a circuit design comprising a plurality of interface instances. One or more buckets for each source instance with...
US20110320992 BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN  
A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit...
US20110197170 Active Net Based Approach for Circuit Characterization  
In a circuit design method, a computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. The computer system extracts, from a layout of the...
US20110185329 GENERATING AND USING ROUTE FIX GUIDANCE  
Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a...
US20110140278 OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION  
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation...
US20140298284 STANDARD CELL DESIGN LAYOUT  
Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is...
US20140181777 AUTOMATIC CLOCK TREE ROUTING RULE GENERATION  
Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a...
US20110093825 TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC  
A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is...
US20110047521 DEVELOPMENT TOOL FOR COMPARING NETLISTS  
System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is...
US20110061038 Pre-Route And Post-Route Net Correlation With Defined Patterns  
A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual...
US20110068423 PHOTODETECTOR WITH WAVELENGTH DISCRIMINATION, AND METHOD FOR FORMING THE SAME AND DESIGN STRUCTURE  
The disclosure relates generally to photodetectors and methods of forming the same, and more particularly to optical photodetectors. The photodetector includes a waveguide having a radius that...
US20120198407 AUTOMATION OF TIE CELL INSERTION, OPTIMIZATION AND REPLACEMENT BY SCAN FLIP-FLOPS TO INCREASE FAULT COVERAGE  
A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding...
US20150067631 DESIGN METHOD OF REPEATER CHIP  
A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying,...
US20110066992 Hardware Description Language (HDL) Generation Systems and Methods For Custom Circuit Boards  
A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from...
US20080307382 COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS  
A method can include allowing a user to place a first wiring harness design component within a wiring harness topology in a wiring harness design workspace, allowing the user to place a first...
US20110016442 Method of Performing Static Timing Analysis Considering Abstracted Cell's Interconnect Parasitics  
An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits...
US20110124193 CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION  
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning...
US20110296366 METHOD OF MAKING ROUTABLE LAYOUT PATTERN USING CONGESTION TABLE  
A method for generating a standard cell layout pattern for standard cell placement in an integrated circuit uses a congestion map. First, congestion zones are identified in a congestion map...
US20140111274 PROGRAMMABLE REVISION CELL ID SYSTEM AND METHOD  
An integrated circuit comprising a plurality of metal programmable revision identification (MPRI) cells, wherein each MPRI cell further comprises a plurality of metal layers, a plurality of vias...
US20130318490 METHOD AND SYSTEM FOR DESIGN AND MODELING OF VERTICAL INTERCONNECTS FOR 3DI APPLICATIONS  
A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that...
US20130227514 Method of Generating RC Technology File  
A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal...
US20110276936 METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY  
A method for analog placement and global routing considering wiring symmetry performs a layout for a circuit which is described by a netlist having a set of devices and wires. First, the method...
US20110289472 LAYOUT QUALITY EVALUATION  
A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at...
US20140327153 STANDARD CELL CONNECTION FOR CIRCUIT ROUTING  
Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal...
US20110093824 TECHNIQUES FOR PERFORMING CONDITIONAL SEQUENTIAL EQUIVALENCE CHECKING OF AN INTEGRATED CIRCUIT LOGIC DESIGN  
A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The...
US20130318489 ACTIVE NET AND PARASITIC NET BASED APPROACH FOR CIRCUIT SIMULATION AND CHARACTERIZATION  
A computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. Active nets are interconnections between circuit components showing a level of...
US20060101367 Design method of semiconductor device and semiconductor device  
In an error analysis step, analysis of an antenna effect error, a timing constraint violation and the like is performed for layout data in which redundant via conversion has been performed. Then,...
US20110231811 MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION  
An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a...
US20110167395 Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements  
A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method...
US20110078649 WAFER LAYOUT ASSISTING METHOD AND SYSTEM  
A wafer layout assisting method is used to assist a circuit designer to estimate the layout related parameter during a circuit designing process. The wafer layout assisting method includes the...
US20110107291 DESIGN SYSTEM AND METHOD THAT, DURING TIMING ANALYSIS, COMPENSATES FOR REGIONAL TIMING VARIATIONS  
Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such...
US20080178139 Use of breakouts in printed circuit board designs  
An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and...
US20140331196 ANALYZING SPARSE WIRING AREAS OF AN INTEGRATED CIRCUIT DESIGN  
A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing...
US20110161901 SYSTEM AND PROCESS FOR AUTOMATIC CLOCK ROUTING IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT  
Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid...
US20090144688 Systems and Methods for Probabilistic Interconnect Planning  
Systems and methods for interconnect planning which utilize probabilistic methodologies. One embodiment comprises a method for planning interconnect models in an integrated circuit design. Nets...
US20140075405 METHOD OF ANALYZING INTERCONNECT FOR GLOBAL CIRCUIT WIRES  
Systems, methods, and other embodiments associated with analyzing interconnects for global wires of a circuit are described. In one embodiment, for a target wire in a circuit design, a method...
US20110254168 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE  
An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a...
US20050144575 Circuit arrangement design method and circuit arrangement design program  
A circuit arrangement design method includes a step of performing a logic conversion of logic, the logic forming a circuit arrangement where a cell arrangement and a connection arrangement between...
US20090265677 INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD  
Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for...
US20100301487 IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY  
A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect...

Matches 1 - 50 out of 346 1 2 3 4 5 6 7 >