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US20110061037 Generating Net Routing Constraints For Place And Route  
A method of generating net routing constraints for nets of an IC design includes generating a file with hashes organized by nets. Each hash has attributes of a net, e.g. net name, length, fanout,...
US20120317529 Rapid Estimation of Temperature Rise in Wires Due to Joule Heating  
A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self...
US20140123091 HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS  
Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided...
US20130036397 Standard Cell Placement Technique For Double Patterning Technology  
A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each...
US20110023001 DYNAMIC RULE CHECKING IN ELECTRONIC DESIGN AUTOMATION  
Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of...
US20140019931 SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION  
Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology...
US20140019932 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DESIGN AND IMPLEMENTATION USING MIXED CELL LIBRARIES  
A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool...
US20080141207 Wiring Design System of Semiconductor Integrated Circuit, Semiconductor Integrated Circuit, and Wiring Design Program  
A wiring design system for semiconductor integrated circuit which realizes a low power consumption in a grid-shaped clock wiring within a semiconductor integrated circuit is provided. A wiring...
US20130219353 CONCURRENT PLACEMENT AND ROUTING USING HIERARCHICAL CONSTRAINTS  
An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for...
US20150067625 MACHINE-LEARNING BASED DATAPATH EXTRACTION  
A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster...
US20140372960 MACHINE-LEARNING BASED DATAPATH EXTRACTION  
A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster...
US20140149957 STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS  
A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement...
US20130174112 METHOD OF GENERATING A BIAS-ADJUSTED LAYOUT DESIGN OF A CONDUCTIVE FEATURE AND METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS  
A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is...
US20140282343 PRIORITIZED SOFT CONSTRAINT SOLVING  
A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be...
US20120174051 Method and System for Generating a Placement Layout of a VLSI Circuit Design  
A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements,...
US20110272782 POWER LAYOUT FOR INTEGRATED CIRCUITS  
A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage...
US20110066993 PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD THEREOF  
A method for merging polygons of a printed circuit board layout system is provided. The system generates PCB files according to the input wiring diagram, and generates polygons and records the...
US20140165020 METHOD OF FORMING A LAYOUT INCLUDING CELLS HAVING DIFFERENT THRESHOLD VOLTAGES, A SYSTEM OF IMPLEMENTING AND A LAYOUT FORMED  
A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the...
US20110320998 LIGHT-EMITTING DIODE SYSTEM DESIGNER  
A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database...
US20110061038 Pre-Route And Post-Route Net Correlation With Defined Patterns  
A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual...
US20150187585 DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERFORMANCE  
A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.
US20130174114 CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST  
In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed...
US20120131534 Automatically Creating Vias in a Circuit Design  
Creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact in a system. Values are stored by a system simulator...
US20150064864 METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY  
A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to...
US20140367760 METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY  
A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to...
US20110113394 PWB Voltage and/or Current Calculation and Verification  
Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on...
US20130332895 METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF  
A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in...
US20110173583 METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF  
A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in...
US20130205272 ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER  
An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the...
US20120284682 Relative Positioning of Circuit Elements in Circuit Design  
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
US20110302546 METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION  
Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be...
US20120297354 METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT  
Some embodiments of the invention provide a method for placing circuit modules in an integrated circuit (“IC”) layout. The method computes a placement metric for the IC layout. In some...
US20110066992 Hardware Description Language (HDL) Generation Systems and Methods For Custom Circuit Boards  
A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from...
US20150199465 BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS  
Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global...
US20110126165 SYSTEM AND PROCESS FOR CLIENT DRIVEN AUTOMATED CIRCUITING AND BRANCH CIRCUIT WIRING  
A computer aided design application modifies a CAD drawing having one or more electrical components by optimizing a plurality of circuits and associated panels, and assigning circuit and panel...
US20130283225 DATAPATH PLACEMENT USING TIERED ASSIGNMENT  
Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified...
US20130097571 METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION  
A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and...
US20150199464 FLOORPLAN ANNEAL USING PERTURBATION OF SELECTED AUTOMATED MACRO PLACEMENT RESULTS  
A method of designing a floorplan for an integrated circuit comprises executing one or more automated placement processes on one or more seed floorplans to generate at least one output floorplan...
US20120066659 METHODS FOR GENERATING DEVICE LAYOUTS BY COMBINING AN AUTOMATED DEVICE LAYOUT GENERATOR WITH A SCRIPT  
Methods for generating a device layout are provided. First, design rules corresponding to a specific technology are received. A selection of at least one element and a parameter value...
US20130007688 GENERATING A CONVERGENT CIRCUIT DESIGN FROM A FUNCTIONAL DESCRIPTION USING ENTITIES HAVING ACCESS TO THE FUNCTIONAL DESCRIPTION AND TO PHYSICAL DESIGN INFORMATION  
A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each...
US20150143322 SWITCH CELL  
A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the...
US20110276936 METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY  
A method for analog placement and global routing considering wiring symmetry performs a layout for a circuit which is described by a netlist having a set of devices and wires. First, the method...
US20110167396 DESIGN PLACEMENT METHOD AND DEVICE THEREFOR  
An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a...
US20140089883 AREA EFFICIENT POWER SWITCH  
A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in...
US20130174113 FLOORPLAN ESTIMATION  
The disclosed invention gives an estimation of the placement location of the units comprising a NoC within the floorplan of a chip. From that, and with knowledge of the number of wires of links...
US20120066658 System And Method For Integrated Circuit Power And Timing Optimization  
A system for selecting gates for an integrated circuit design may include at least one processing device configured to identify gates of the integrated circuit design having a slack value less...
US20140053123 DENSITY-BASED INTEGRATED CIRCUIT DESIGN ADJUSTMENT  
The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a...
US20150234971 APPORTIONING SYNTHESIS EFFORT FOR BETTER TIMING CLOSURE  
Timing for a critical path of a circuit design is optimized by splitting up the path so the synthesis effort to solve the path is appropriately apportioned. Selected nodes of the path are made...
US20140282340 METHOD FOR PROVISIONING DECOUPLING CAPACITANCE IN AN INTEGRATED CIRCUIT  
A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance...
US20130074028 METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS  
A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to...