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US20150186589 |
SYSTEM FOR AND METHOD OF PLACING AND ROUTING CLOCK STATIONS USING VARIABLE DRIVE-STRENGTH CLOCK DRIVERS BUILT OUT OF A SMALLER SUBSET OF BASE CELLS FOR HYBRID TREE-MESH CLOCK DISTRIBUTION NETWORKS
Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution... |
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US20130341720 |
IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS
A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject... |
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US20140007035 |
Method and Apparatus to Perform Footprint-Based Optimization Simultaneously with Other Steps
A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the... |
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US20140359547 |
HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS
Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided... |
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US20140040847 |
SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES
One aspect provides a system for generating a layout for dual patterning technologies. In one embodiment, the system includes: (1) a deterministic boundary interconnect feature generator... |
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US20130086543 |
MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN
A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global... |
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US20130159955 |
DYNAMIC PIN ACCESS MAXIMIZATION FOR MULTI-PATTERNING LITHOGRAPHY
A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative... |
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US20140380259 |
LAYOUT MIGRATION WITH HIERARCHICAL SCALE AND BIAS METHOD
A method for migrating a hierarchical layout between manufacturing processes is accomplished without specification of a technology file and design rules. Different scaling factors and bias values... |
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US20110055784 |
MULTI-THREADED GLOBAL ROUTING
Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During... |
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US20150012901 |
FIXED-OUTLINE FLOORPLANNING APPROACH FOR MIXED-SIZE MODULES
A fixed-outline floorplanning approach for mixed-size modules is disclosed. Firstly, evenly distribute mixed-size circuit modules to whole chip area based on different requirements such as... |
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US20100306729 |
SYSTEM AND METHOD FOR GENERATING FLAT LAYOUT
The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a... |
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US20110035717 |
Design Optimization for Circuit Migration
An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium... |
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US20130285190 |
Layout of a MOS Array Edge with Density Gradient Smoothing
A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered... |
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US20110140278 |
OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation... |
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US20120102445 |
IMPLEMENTING ENHANCED RLM CONNECTIVITY ON A HIERARCHICAL DESIGN WITH TOP LEVEL PIPELINE REGISTERS
A method, system, and computer program product are provided for implementing enhanced random logic macro (RLM) connectivity on a hierarchical design on an integrated circuit chip with top-level... |
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US20120290995 |
CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST
In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed... |
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US20120131534 |
Automatically Creating Vias in a Circuit Design
Creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact in a system. Values are stored by a system simulator... |
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US20150186588 |
MULTILEVEL VIA PLACEMENT WITH IMPROVED YIELD IN DUAL DAMASCENE INTERCONNECTION
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via... |
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US20150064864 |
METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY
A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to... |
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US20140367760 |
METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY
A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to... |
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US20130097573 |
ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER
An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the... |
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US20120240092 |
METHOD AND DEVICE FOR REORDERING SCAN CHAINS CONSIDERING PLAN GROUPS
Provided in the present invention is a reconfiguration method and device for scan chains with the planned unit taken into consideration, wherein said reconfiguration method of the scan chains... |
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US20150040091 |
METHODS FOR MODIFYING AN INTEGRATED CIRCUIT LAYOUT DESIGN
Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit... |
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US20140253220 |
ELECTRONIC FUSE CELL AND ARRAY
Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first... |
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US20130001732 |
PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL
CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in... |
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US20130061195 |
Methods and Apparatuses for Circuit Design and Optimization
In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or... |
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US20140304671 |
MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN
A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell... |
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US20110307854 |
MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN
A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell... |
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US20130256898 |
Optimizing Layout of Irregular Structures in Regular Layout Context
A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular... |
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US20110161907 |
Practical Approach to Layout Migration
The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first... |
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US20150213183 |
System and Method for Designing Cell Rows
A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard... |
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US20140115553 |
System and Method for Designing Cell Rows
A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard... |
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US20090183134 |
DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES
A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a... |
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US20060129955 |
Printed circuit board development cycle using probe location automation and bead probe technology
Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probes insertion in a PCB tester fixture are presented. A probe location algorithm predictably... |
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US20130075869 |
Chip Comprising a Fill Structure
A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge. |
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US20130069169 |
ECO LOGIC CELL AND DESIGN CHANGE METHOD USING ECO LOGIC CELL
The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks... |
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US20110302544 |
POST-PLACEMENT CELL SHIFTING
A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles.... |
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US20150082265 |
DESIGN STRUCTURE FOR CHIP EXTENSION
One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second... |
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US20110320997 |
Delay-Cell Footprint-Compatible Buffers
A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and... |
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US20110265055 |
HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT
A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a... |
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US20120273899 |
SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET... |
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US20120054707 |
CONE-AWARE SPARE CELL PLACEMENT USING HYPERGRAPH CONNECTIVITY ANALYSIS
Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones,... |
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US20130083577 |
OFFLINE LOW VOLTAGE DC OUTPUT CIRCUIT WITH INTEGRATED FULL BRIDGE RECTIFIERS
The present disclosure discloses an offline low voltage DC output circuit with integrated full bridge rectifiers. The offline low voltage DC output circuit comprises two depletion high voltage... |
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US20140359546 |
STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SYNTHESIS OF AN INTEGRATED CIRCUIT
Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative... |
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US20120112244 |
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures... |
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US20130125077 |
METHOD FOR OPTIMISING CELL VARIANT SELECTION WITHIN A DESIGN PROCESS FOR AN INTEGRATED CIRCUIT DEVICE
A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an... |
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US20130185690 |
Automatically Modifying a Circuit Layout to Perform Electromagnetic Simulation
Automatically modifying a layout to perform circuit simulation. Initially, a first layout of the electronic system may be received or stored. A second layout of the electronic system may be... |
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US20080189671 |
HDL Design Structure for Integrating Test Structures into an Integrated Circuit Design
A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually... |
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US20140167815 |
AREA RECONFIGURABLE CELLS OF A STANDARD CELL LIBRARY
An integrated circuit using area reconfigurable cells of a standard cell library includes standard cells placed adjacent with one another in rows and columns. Each of the standard cells has a... |
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US20080301613 |
DESIGNING WIRING HARNESSES
A method of designing a wiring harness using a wiring harness design tool can include allowing a first user to access and edit a first wiring harness design component in a wiring harness design... |