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US20130159954 DESIGN METHOD OF ON-BOARD WIRING  
A design method of on-board wiring for a designed circuit includes determining a severity as a crosstalk prevention index for a pair of wires based on a generated noise level of a damaging side...
US20110246957 PIN PLACEMENT DETERMINING METHOD  
A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a...
US20140250415 CROSSTALK ANALYSIS METHOD  
One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program;...
US20120317530 SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE  
A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design...
US20150143318 DETERMINATION OF ELECTROMIGRATION SUSCEPTIBILITY BASED ON HYDROSTATIC STRESS ANALYSIS  
Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is...
US20130198711 POWER LAYOUT FOR INTEGRATED CIRCUITS  
A method for a power layout of an integrated circuit. The method includes providing at least one unit power cell. The unit power cell includes at least one power grid cell. Each power grid cell...
US20050246672 Differential trace pair coupling verification tool  
A method for verifying coupling in a differential trace pair group includes reading victim properties of a victim differential trace pair and culprit properties of a plurality of culprit...
US20110161905 Layout Electromagnetic Extraction For High-Frequency Design And Verification  
Embodiments of the present invention provide a method of circuit design and circuit simulation. A method for electromagnetic simulation of passive structures of a circuit design is disclosed. The...
US20140365986 Method Of Optimizing Capacitive Couplings In High-Capacitance Nets In Simulation Of Post-Layout Circuits  
A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method...
US20120060137 Method for designing wiring topology for electromigration avoidance and fabrication method of integrate circuits including said method  
A method for designing wiring topology for electromigration avoidance, which is composed of multiple sources, multiple sinks and multiple wires, is disclosed. The steps of said method to get an...
US20140109030 Method of Determining Electromigration (EM) Lifetimes and Lifetime Criteria  
Methods are described for performing detailed Technology Computer Aided Design (TCAD) simulations of electromigration (EM) failure in a standard test structure suitable for the simulation of...
US20140258959 SUPPORT TECHNIQUE  
A present design support method includes: arranging capacitance cells in an entire area of a cell arrangement area of a semiconductor integrated circuit , before arranging logic cells; upon...
US20140040846 CROSSTALK ANALYSIS METHOD  
An embodiment of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program;...
US20080184179 INTEGRATED CIRCUIT DESIGNING DEVICE, INTEGRATED CIRCUIT DESIGNING METHOD, AND INTEGRATED CIRCUIT DESIGNING PROGRAM  
Shielded clock wiring used in an integrated circuit is designed by storing a table of identifiers of shielded clock wiring usable in the integrated circuit, storing dividing rule information in...
US20070094630 Power grid design in an integrated circuit  
An aspect of the present invention computationally determines the metal density of each metal layer supporting a power grid structure providing power to the elements of an integrated circuits. The...
US20110320995 Noise Analysis Designing Method  
To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product...
US20110035716 DESIGN SUPPORT PROGRAM, DESIGN SUPPORT DEVICE, AND DESIGN SUPPORT METHOD  
A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a...
US20150227669 CIRCUIT-LEVEL ABSTRACTION OF MULTIGATE DEVICES USING TWO-DIMENSIONAL TECHNOLOGY COMPUTER AIDED DESIGN  
A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the...
US20060190866 Resistance extraction for hierarchical circuit artwork  
In one embodiment, a method is disclosed for extracting resistance from hierarchical circuit artwork having parent and child circuit blocks. In accordance with the method, and for each child...
US20080134109 Analog Design Retargeting  
An analog retargeting system and method are disclosed for converting a circuit from a source technology to a target technology. Thus, an analog circuit in a source technology can be converted to...
US20130201726 RESONANT POWER CONVERTER HAVING SWITCHED SERIES TRANSFORMER  
A multi-transformer LLC (resonant) power converter having at least two transformers including a first T1 and a second transformer T2 in series includes a switch network configured for receiving...
US20140351779 INTEGRATED CIRCUIT (IC) DESIGN METHOD WITH ENHANCED CIRCUIT EXTRACTION MODELS  
A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various...
US20120260225 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits  
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on...
US20130305204 HIERARCHICAL FEATURE EXTRACTION FOR ELECTRICAL INTERACTION CALCULATIONS  
A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a...
US20130047130 EARLY NOISE DETECTION AND NOISE AWARE ROUTING IN CIRCUIT DESIGN  
A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a...
US20120254816 NOISE REDUCTION USING FEEDBACK TO A WIRE SPREADER ROUTER  
A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line...
US20140317585 CROSSTALK ANALYSIS METHOD  
An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program;...
US20080109773 Analyzing Impedance Discontinuities In A Printed Circuit Board  
Analyzing impedance discontinuities in a printed circuit board, where the printed circuit board is made up of layers of dielectric substrate having signal traces and power planes disposed upon the...
US20080184186 INTEGRATED CIRCUIT DESIGN FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT  
A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between...
US20070033558 Method and system for reshaping metal wires in VLSI design  
A method and system for representing metal wires in Very Large Scale Integration (VLSI) circuit design in a simplified form. A pair of metal wires is considered at a time. A plurality of Piece...
US20080155483 Database-aided circuit design system and method therefor  
A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage...
US20050251776 INTEGRATED CIRCUIT DESIGN SYSTEM  
An integrated circuit design system has a second interface for displaying a plurality of description instructions corresponding to a specific integrated circuit according to a variety of display...
US20100229141 TIMING VIOLATION DEBUGGING INSIDE PLACE AND ROUTE TOOL  
A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally...
US20070157133 Circuit network analysis using algebraic multigrid approach  
This application describes techniques for applying an algebraic multigrid method to analysis of circuit networks with irregular and regular circuit patterns. Adaptive processing may be applied to...
US20080028353 METHOD FOR TREATING PARASITIC RESISTANCE, CAPACITANCE, AND INDUCTANCE IN THE DESIGN FLOW OF INTEGRATED CIRCUIT EXTRACTION, SIMULATIONS, AND ANALYSES  
An extraction, simulation, and analysis combined method is employed to account for the parasitic couplings from interconnect wires. Variations of parasitic resistance, capacitance, and inductance...
US20070220459 Capacitance extraction of intergrated circuits with floating fill  
The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of...
US20070266360 Metal Thickness Simulation for Improving RC Extraction Accuracy  
An integrated circuit (IC) design method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a...
US20080077892 Circuit unit designing apparatus, circuit unit designing method, and circuit unit designing program  
A circuit unit designing apparatus configured to design a circuit unit in which, on a substrate, a plurality of circuit components are disposed, includes a circuit designing part carrying out...
US20070204245 Method for accelerating the RC extraction in integrated circuit designs  
The present invention provides a system and method for accelerating the resistance and capacitance (RC) extraction process by performing parallel and distributed processing. The method includes...
US20150046892 Cross-Talk Noise Computation Using Mixed Integer Linear Program Problems And Their Solutions  
A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a...
US20150046891 Cross-Talk Noise Computation Using Mixed Integer Linear Program Problems And Their Solutions  
A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a...
US20110180942 INTERCONNECTION STRUCTURE  
An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with...
US20080148213 ROUTING METHOD FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT  
A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between...
US20080072182 STRUCTURED AND PARAMETERIZED MODEL ORDER REDUCTION  
Model-order reduction techniques are described for RLC circuits modeling the VLSI layouts. A structured model order reduction is developed to preserve the block-level sparsity, hierarchy and...
US20080022242 Board layout check apparatus and board layout check method  
There is provided a board layout check apparatus for checking whether or not a guard wiring is appropriately formed, wherein a place which must be corrected is clearly displayed. The board layout...
US20050114807 Cross talk analysis methodology and solution  
Disclosed is an analysis methodology and equivalent RLC circuits that accurately model the effects of packaging circuitry, bond wire circuitry and other sources of cross talk within an...
US20140137063 CIRCUIT NOISE EXTRACTION USING FORCED INPUT NOISE WAVEFORM  
Techniques for use in integrated circuit design systems for extracting noise threshold data for selected cells. For example, a method comprises the following steps. A cell is selected from one or...
US20060031055 Branch merge reduction of RLCM networks  
Various tools and techniques are provided for reducing an original circuit network into a simpler, realizable RCLM circuit network. Branches of the original network are merged to reduce its total...
US20120131532 Substrate Noise Assessment Flow In Mixed-Signal And SOC Designs  
A substrate noise checking methodology is disclosed. A tool is provided that aggregates the noise effect of one or more of digital noise injectors on one or more receptors. The tool also provides...
US20060117283 Integrated circuit verification method, verification apparatus, and verification program  
A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical...

Matches 1 - 50 out of 240 1 2 3 4 5 >